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Optimal Self-Testing Embedded Parity Checkers
March 1998 (vol. 47 no. 3)
pp. 313-321

Abstract—This paper presents a new simple and straightforward method for designing Self-Testing Embedded (STE) parity checkers. The building block is the two-input XOR gate. During normal, fault-free operation, each XOR gate receives all possible input vectors. The great advantage of the proposed method is that it is the only one that gives, in a simple and straightforward way, optimal STE realizations with respect to the cost (number of XOR gates) and the speed (number of XOR gate levels).

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Index Terms:
Parity tree, parity checker, two-rail checker, self-testing , embedded self-testing circuits.
Citation:
Dimitris Nikolos, "Optimal Self-Testing Embedded Parity Checkers," IEEE Transactions on Computers, vol. 47, no. 3, pp. 313-321, March 1998, doi:10.1109/12.660167
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