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Dimitris Nikolos, "Optimal SelfTesting Embedded Parity Checkers," IEEE Transactions on Computers, vol. 47, no. 3, pp. 313321, March, 1998.  
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@article{ 10.1109/12.660167, author = {Dimitris Nikolos}, title = {Optimal SelfTesting Embedded Parity Checkers}, journal ={IEEE Transactions on Computers}, volume = {47}, number = {3}, issn = {00189340}, year = {1998}, pages = {313321}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.660167}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Optimal SelfTesting Embedded Parity Checkers IS  3 SN  00189340 SP313 EP321 EPD  313321 A1  Dimitris Nikolos, PY  1998 KW  Parity tree KW  parity checker KW  tworail checker KW  selftesting KW  embedded selftesting circuits. VL  47 JA  IEEE Transactions on Computers ER   
Abstract—This paper presents a new simple and straightforward method for designing SelfTesting Embedded (STE) parity checkers. The building block is the twoinput XOR gate. During normal, faultfree operation, each XOR gate receives all possible input vectors. The great advantage of the proposed method is that it is the only one that gives, in a simple and straightforward way, optimal STE realizations with respect to the cost (number of XOR gates) and the speed (number of XOR gate levels).
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