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Issue No.03 - March (1998 vol.47)
pp: 305-312
ABSTRACT
<p><b>Abstract</b>—This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.</p>
INDEX TERMS
Memory BIST, Markov chain, signal probability, detection probability, memory prelogic, memory postlogic.
CITATION
Jacob Savir, "Random Pattern Testability of Memory Control Logic", IEEE Transactions on Computers, vol.47, no. 3, pp. 305-312, March 1998, doi:10.1109/12.660166
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