Issue No.03 - March (1998 vol.47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.660163
<p><b>Abstract</b>—We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. In [<ref rid="bibt02734" type="bib">4</ref>], Oklobdzija et al. suggested a new approach, the Three-Dimensional Method (TDM), for Partial Product Reduction Tree (PPRT) design that produces multipliers that outperform the current best designs. The goal of TDM is to produce a minimum delay PPRT using full adders. This is done by carefully modeling the relationship of the output delays to the input delays in an adder and, then, interconnecting the adders in a globally optimal way. Oklobdzija et al. suggested a good heuristic for finding the optimal PPRT, but no proofs about the performance of this heuristic were given. We provide a formal characterization of optimal PPRT circuits and prove a number of properties about them. For the problem of summing a set of input bits within the minimum delay, we present an algorithm that produces a minimum delay circuit in time linear in the size of the inputs. Our techniques allow us to prove tight lower bounds on multiplier circuit delays. These results are combined to create a program that finds optimal TDM multiplier designs. Using this program, we can show that, while the heuristic used in[<ref rid="bibt02734" type="bib">4</ref>] does not always find the optimal TDM circuit, it performs very well in terms of overall PPRT circuit delay. However, our search algorithms find better PPRT circuits for reducing the delay of the entire multiplier.</p>
Multiplier design, partial product reduction, algorithms, circuit design.
Paul F. Stelling, Charles U. Martel, Vojin G. Oklobdzija, R. Ravi, "Optimal Circuits for Parallel Multipliers", IEEE Transactions on Computers, vol.47, no. 3, pp. 273-285, March 1998, doi:10.1109/12.660163