
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Paul F. Stelling, Charles U. Martel, Vojin G. Oklobdzija, R. Ravi, "Optimal Circuits for Parallel Multipliers," IEEE Transactions on Computers, vol. 47, no. 3, pp. 273285, March, 1998.  
BibTex  x  
@article{ 10.1109/12.660163, author = {Paul F. Stelling and Charles U. Martel and Vojin G. Oklobdzija and R. Ravi}, title = {Optimal Circuits for Parallel Multipliers}, journal ={IEEE Transactions on Computers}, volume = {47}, number = {3}, issn = {00189340}, year = {1998}, pages = {273285}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.660163}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Optimal Circuits for Parallel Multipliers IS  3 SN  00189340 SP273 EP285 EPD  273285 A1  Paul F. Stelling, A1  Charles U. Martel, A1  Vojin G. Oklobdzija, A1  R. Ravi, PY  1998 KW  Multiplier design KW  partial product reduction KW  algorithms KW  circuit design. VL  47 JA  IEEE Transactions on Computers ER   
Abstract—We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. In [4], Oklobdzija et al. suggested a new approach, the ThreeDimensional Method (TDM), for Partial Product Reduction Tree (PPRT) design that produces multipliers that outperform the current best designs. The goal of TDM is to produce a minimum delay PPRT using full adders. This is done by carefully modeling the relationship of the output delays to the input delays in an adder and, then, interconnecting the adders in a globally optimal way. Oklobdzija et al. suggested a good heuristic for finding the optimal PPRT, but no proofs about the performance of this heuristic were given. We provide a formal characterization of optimal PPRT circuits and prove a number of properties about them. For the problem of summing a set of input bits within the minimum delay, we present an algorithm that produces a minimum delay circuit in time linear in the size of the inputs. Our techniques allow us to prove tight lower bounds on multiplier circuit delays. These results are combined to create a program that finds optimal TDM multiplier designs. Using this program, we can show that, while the heuristic used in[4] does not always find the optimal TDM circuit, it performs very well in terms of overall PPRT circuit delay. However, our search algorithms find better PPRT circuits for reducing the delay of the entire multiplier.
[1] T.H. Cormen,C.E. Leiserson, and R.L. Rivest,Introduction to Algorithms.Cambridge, Mass.: MIT Press/McGrawHill, 1990.
[2] L. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349356, 1965.
[3] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[4] V.G. Oklobdzija, D. Villeger, and S.S. Liu, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach," IEEE Trans. Computers, vol. 45, no. 3, pp. 294305, Mar. 1996.
[5] V.G. Oklobdzija and D. Villeger, "Optimization and Analysis of a CarryPropagate Adder Under the NonUniform Signal Arrival Profile," in preparation.
[6] V.G. Oklobdzija and D. Villeger, "Improving Multiplier Design by Using Improved Column Compression Tree and Optimized Final Adder in CMOS Technology," IEEE Trans. VLSI Systems, vol. 3, no. 2, pp. 292301, June 1995.
[7] M.S. Paterson, N. Pippenger, and U. Zwick, "Faster Circuits and Shorter Formulae for Multiple Addition, Multiplication and Symmetric Boolean Functions," Proc. 31st Foundations of Computer Science, pp. 642650, 1990.
[8] M.S. Paterson, N. Pippenger, and U. Zwick, "Optimal Carry Save Networks," Boolean Functional Complexity: Selected Papers from the LMS Symp., Durham 1990. Cambridge Univ. Press, 1992.
[9] M.S. Paterson and U. Zwick, "Shallow Multiplication Circuits and Wise Financial Investments," Proc. 24th Symp. Theory of Computing, pp. 429437, 1992.
[10] M.R. Santoro, "Design and Clocking of VLSI Multipliers," PhD dissertation, Technical Report no. CSLTR89397, 1989.
[11] P. Song and G. De Micheli, “Circuit and Architecture TradeOffs for HighSpeed Multiplication,” IEEE J. Solid State Circuits, vol. 26, no. 9, Sept. 1991.
[12] W.J. Stenzel, "A Compact High Speed Parallel Multiplication Scheme," IEEE Trans. Computers, vol. 26, pp. 948957, 1977.
[13] V.G. Oklobdzija and P. Stelling, "Design Strategies for the Final Adder in a Parallel Multiplier," Conf. Record 29th Ann. Asilomar Conf. Signals, Systems, and Computers, vol. 1, pp. 591595, Oct. 1996.
[14] P. Stelling and V.G. Oklobdzija, "Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier," J.VLSI Signal Processing, vol. 14, no. 3, 1996.
[15] P.F. Stelling and V.G. Oklobdzija, "Implementing MultiplyAccumulate Operation in Multiplication Time," Proc. 13th Symp. Computer Arithmetic, pp. 99106, 1997.
[16] P.F. Stelling and V.G. Oklobdzija, "Optimal Designs for Multipliers and MultiplyAccumulators," Proc. 15th IMACS World Congress 1997 on Scientific Computation, Modelling, and Applied Mathematics, vol. 4, Artificial Intelligence and Computer Science, A. Sydow, ed., pp. 739744.Berlin: Wissenschaft und Technik Verlag, 1997.
[17] E. Swartzlander, Computer Arithmetic, vols. 1&2. IEEE CS Press, 1990.
[18] C.S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Trans. Electronic Computers, vol. 13, pp. 1417, 1964.
[19] 1.0Micron ArrayBased Products Databook. LSI Logic Corporation, 1991.