This Article 
 Bibliographic References 
 Add to: 
ATPG for Heat Dissipation Minimization During Test Application
February 1998 (vol. 47 no. 2)
pp. 256-262

Abstract—A new automatic test pattern generator (ATPG) algorithm is proposed that reduces switching activity (between successive test vectors) during test application. The main objective is to permit safe and inexpensive testing of low power circuits and bare die that might otherwise require expensive heat removal equipment for testing at high speeds. Three new cost functions, namely, transition controllability, observability, and test generation costs, have been defined. It has been shown, for a fanout free circuit under test, that the transition test generation cost for a fault is the minimum number of transitions required to test a given stuck-at fault. The proposed algorithm has been implemented and the generated tests are compared with those generated by a standard PODEM implementation for the larger ISCAS85 benchmark circuits. The results clearly demonstrate that the tests generated using the proposed ATPG can decrease the average number of (weighted) transitions between successive test vectors by a factor of 2 to 23.

[1] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design.New York: Computer Science Press, 1990.
[2] S. Bhatia and N.K. Jha, "Synthesis for Parallel Scan: Applications to Partial Scan and Robust Path-Delay Fault Testability," IEEE Trans. Computer-Aided Design of Integrated Circuit and System, vol. 15, Feb. 1996.
[3] S. Chakravarty and V.P. Dabholkar, "Two Techniques for Minimizing Power Dissipation in Scan Circuits During Test Application," Proc. Third Asian Test Symp., 1994.
[4] D.A. Doane and P.D. Franzon, Multchip Module Technologies and Alternatives: The Basics.New York: Van Nostrand Reinhold, 1992.
[5] P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. Computers, vol. 30, no. 3, Mar. 1981.
[6] L.H. Goldstein, Controllability/Observability Analysis of Digital Circuits IEEE Trans. Circuits and Systems, vol. 26, pp. 685-693, 1979.
[7] L.H. Goldstein and E.L. Thigpen, "SCOAP: Sandia Controllability/Observability Analysis Program," Proc. Design Automation Conf., pp. 190-196, 1980.
[8] R. Gupta, R. Gupta, and M.A. Breuer, The BALLAST Methodology for Structured Partial Scan Design IEEE Trans. Computers, vol. 39, pp. 538-544, 1990.
[9] D.K. Pradhan and J. Saxena, "Design for Testablility Scheme to Reduce Test Application in Full Scan," Proc. VLSI Testing Symp., pp. 55-60, 1992.
[10] A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, “On Average Power Dissipation and Random Pattern Testability of CMOS Combinational Logic Networks,” Proc. IEEE/ACM Int'l Conf. Computer Aided Design, pp. 402-407, 1992.
[11] S. Wang and S.K. Gupta, "ATPG for Heat Dissipation Minimization During Test Application," Proc. IEEE Int'l Test Conf., pp. 250-258, Oct. 1994.
[12] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1994.
[13] Y. Zorian Private Communication.
[14] Y. Zorian, "A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary Scan," Proc. IEEE Int'l Conf. Computer Design, 1992.
[15] Y. Zorian, "A Distributed BIST control scheme for Complex VLSI devices," Proc. 11th IEEE VLSI Test Symp., 1993, pp. 4-9.

Index Terms:
Combinational ATPG, switching activity, heat dissipation, PODEM, testing.
Seongmoon Wang, Sandeep K. Gupta, "ATPG for Heat Dissipation Minimization During Test Application," IEEE Transactions on Computers, vol. 47, no. 2, pp. 256-262, Feb. 1998, doi:10.1109/12.663775
Usage of this product signifies your acceptance of the Terms of Use.