This Article 
 Bibliographic References 
 Add to: 
An Approach to Designing Modular Extensible Linear Arrays for Regular Algorithms
February 1998 (vol. 47 no. 2)
pp. 212-216

Abstract—The purpose of this paper is to describe a new method to design unidirectional modular extensible linear arrays for regular algorithms. The time complexity of our method is polynomial and depends only on the number of dimensions of the regular algorithm. The designed linear array is asymptotically optimal in space and time.

[1] H.T. Kung and C.E. Leiserson, "Systolic Arrays (for VLSI)," Proc. Sparse Matrix Symp., pp. 256-282. Soc. for Industrial and Applied Math, 1978.
[2] I.V. Ramakrishnan and P.J. Varman, "Modular Matrix Multiplication on a Linear Array," IEEE Trans. Computers, vol. 33, no. 11, pp. 952-958, Nov. 1984.
[3] P.J. Varman and I.V. Ramakrishnan, "Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays," IEEE Trans. Computers, vol. 35, no. 11, pp. 989-996, Nov. 1986.
[4] V.K.P. Kuman and Y.C. Tsai,“On synthesizing optimal family of linear systolic arrays for matrix multiplication,” IEEE Trans. Computers, vol. 40, no. 6, pp. 770-774, June 1991.
[5] J.F. Myoupo, "A Way of Deriving Linear Systolic Arrays from a Mathematical Algorithm Description: Case of the Warshall-Floyd Algorithm," Proc. Int'l Conf. Parallel Processing, pp. I.575-I.579, 1991.
[6] S.K. Rao,“Regular iterative algorithms and their implementations on processor arrays,” PhD thesis, Stanford Univ., 1985.
[7] P.Z. Lee and Z.M. Kedem,“Synthesizing linear array algorithms from nested for loop algorithms,” IEEE Trans. Computers, vol. 37, pp. 1,578-1,598, Dec. 1988.
[8] W. Shang and J.A.B. Fortes, "On Time Mapping of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays," IEEE Trans. Parallel and Distributed Systems, vol. 3, no. 5, pp. 350-363, May 1992.
[9] K.N. Ganapathy and B.W. Wah, "Synthesizing Optimal Lower Dimensional Processor Arrays," Proc. Int'l Conf. Parallel Processing, pp. III.96-III.103, 1992.
[10] R. Varadarajan and B. Ravichandran, "Refinement Based Techniques for Mapping Nested Loop Algorithms onto Linear Systolic Arrays," Integration, The VLSI J., vol. 14, pp. 249-277, Feb. 1993.
[11] P. Quinton, “Automatic Synthesis of Systolic Arrays from Uniform Recurrent Equations,” Proc. 11th Ann. Int'l Symp. Computer Architecture, pp. 208-214, June 1984.
[12] M. Wolf and M. Lam, “A Loop Transformation Theory and an Algorithm to Maximize Parallelism,” IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 4, Oct. 1991.
[13] W. Shang and J.A.B. Fortes, "Independent Partitioning of Algorithms with Uniform Dependencies," IEEE Trans. Computers, vol. 41, no. 2, pp. 190-206, Feb. 1992.
[14] J.C. Tsay and P.Y. Chang, "Designing Lower Dimensional Regular Arrays for Algorithms with Uniform Dependencies," J. Parallel and Distributed Computing, vol. 33, pp. 24-32, 1996.
[15] P.Y. Chang, "Design of Efficient Regular Arrays for Matrix Algorithms," PhD thesis, National Chiao Tung Univ., Hsinchu, Taiwan, R.O.C., 1995.
[16] F.T. Leighton,Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes.San Mateo, Calif.: Morgan Kaufmann, 1992.

Index Terms:
Algorithm transformation, conflict-free mapping, data dependency, linear array, modular extensible, optimal spacetime mapping, regular algorithm, systolic array, unimodular matrix, VLSI.
Pen-Yuang Chang, Jong-Chuang Tsay, "An Approach to Designing Modular Extensible Linear Arrays for Regular Algorithms," IEEE Transactions on Computers, vol. 47, no. 2, pp. 212-216, Feb. 1998, doi:10.1109/12.663767
Usage of this product signifies your acceptance of the Terms of Use.