This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Floating Steiner Trees
February 1998 (vol. 47 no. 2)
pp. 197-211

Abstract—We study the reproducing placement problem, which finds application in layout-driven logic synthesis. In each phase, a module (or gate) is decomposed into two (or more) simpler modules. The goal is to find a "good" placement in each phase. The problem, being iterative in nature, requires an iterative algorithm. In solving the RPP, we introduce the notion of minimum floating Steiner trees (MFST). We employ an MFST algorithm as a central step in solving the RPP. A Hanan-like theorem is established for the MFST problem, and two approximation algorithms are proposed. Experiments on commonly employed benchmarks verify the effectiveness of the proposed technique.

[1] P. Berman, U. Foessmeier, M. Karpinski, M. Kaufmann, and A.Z. Zelikovsky, "Approaching the 5/4-Approximation for Rectilinear Steiner Trees," Technical Report WSI-94-06, Wilhelm Schickard-Institut für Informatik, 1994.
[2] C. Chiang, M. Sarrafzadeh, and C.K. Wong, "An Optimal Algorithm for Rectilinear Steiner Trees for Channels with Obstacles," Int'l J. Circuit Theory and Applications, special issue on fundamental methods in computer-aided circuit design, vol. 19, no. 6, pp. 551-563, Dec. 1991.
[3] C.K. Cheng and E.S. Kuh, "Module Placement Based on Resistive Network Optimization," IEEE Trans. Computer-Aided Design, vol. 3, no. 3, pp. 218-225, 1984.
[4] D.I. Cheng, S. Chang, and M. Marek-Sadowska, "Partitioning Combinational Circuits in Graph and Logic Domains," Proc. Synthesis and Simulation Meeting and Int'l Interchange (SASIMI-93), 1993.
[5] C. Chiang, M. Sarrafzadeh, and C.K. Wong, "Global Routing Based on Steiner Min-Max Trees," IEEE Trans. Computer-Aided Design, vol. 9, no. 12, pp. 1,315-1,325, 1990.
[6] C. Chiang, M. Sarrafzadeh, and C.K. Wong, "An Optimal Algorithm for Constructing a Steiner Tree in a Switchbox, Part I: Fundamental Theory and Application," IEEE Trans. Circuits and Systems, vol. 39, no. 6, 1992.
[7] C. Chiang, C.K. Wong, and M. Sarrafzadeh, "A Weighted Steiner Tree-Based Global Router with Simultaneous Length and Density Minimization," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1,461-1,469, Dec. 1994.
[8] J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh, and C.K. Wong, "Provably Good Performance-Driven Global Routing," IEEE Trans. Computer-Aided Design, vol. 11, no. 6, pp. 739-752, June 1992.
[9] A.E. Dunlop and B.W. Kernighan, "A Procedure for Placement of Standard Cell VLSI Circuits," IEEE Trans. Computer-Aided Design, vol. 4, no. 1, pp. 92-98, Jan. 1985.
[10] M.R. Garey and D.S. Johnson, "The Rectilinear Steiner Tree Problem Is NP-Complete," SIAM J. Applied Math., vol. 32, no. 4, pp. 826-834, Apr. 1977.
[11] G. Georgakopoulos and C.H. Papadimitriou, "The 1-Steiner Tree Problem," J. Algorithms, vol. 8, pp. 122-130, 1987.
[12] M. Hanan, "On Steiner's Problem with Rectilinear Distance," SIAM J. Applied Math., vol. 14, no. 2, pp. 255-265, Feb. 1966.
[13] A. Kahng and G. Robins, "A New Class of Iterative Steiner Tree Heuristics with Good Performance," IEEE Trans. Computer-Aided Design, vol. 11, no. 7, pp. 893-902, 1992.
[14] J.M. Kleinhans, G. Sigl, F.M. Johannes, and K.J. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization," IEEE Trans. Computer-Aided Design, vol. 10, no. 3, p. 365, 1991.
[15] D.T. Lee and C.K. Wong, "Voronoi Diagrams in L1 (L∞) Metrics with 2-Dimensional Storage Applications," SIAM J. Computing, vol. 9, no. 1, pp. 200-211, Feb. 1980.
[16] S. Liu, K. Pan, and M. Pedram, "Alleviating Routing Congestion by Combining Logic Resynthesis and Linear Placement," Proc. European Design Automation Conf., pp. 578-582, 1993.
[17] M. Pedram and N. Bhat, "Layout Driven Technology Mapping," Proc. Design Automation Conf., pp. 99-105, 1991.
[18] F.P. Preparata and M.I. Shamos, Computational Geometry. Springer-Verlag, 1985.
[19] M. Sarrafzadeh and C.K. Wong, An Introduction to Physical Design. McGraw-Hill, 1996.
[20] M. Sarrafzadeh and C.K. Wong, "Bottleneck Steiner Trees in the Plane," IEEE Trans. Computers, vol. 41, no. 3, pp. 370-374, Mar. 1992.
[21] M. Sarrafzadeh and C.K. Wong, “Hierarchical Steiner Tree Construction in Uniform Orientations,” IEEE Trans. Computer-Aided-Design, vol. 11, pp. 1095-1103, 1992.
[22] C. Sechen and A. Sangiovanni-Vincentelli, "Timberwolf3.2: A New Standard Cell Placement and Global Routing Package," Proc. 23rd ACM/IEEE Design Automation Conf., pp. 432-439, 1986.
[23] K. Shahookar and P. Mazumder, "VLSI Cell Placement Techniques," ACM Computing Surveys, vol. 23, no. 2, pp. 143-220, June 1991.
[24] G.E. Téllez and M. Sarrafzadeh, "On Rectilinear Distance-Preserving Trees," Proc. Int'l Symp. Circuits and Systems, vol. 1, pp. 163-166, 1995.
[25] R.-S. Tsay, "Exact Zero Skew," Proc. Int'l Conf. Computer-Aided Design, pp. 336-339, 1991.
[26] M. Sarrafzadeh and M. Wang, "NRG: Global and Detailed Placement," Proc. Int'l Conf. Computer-Aided-Design, Nov. 1997.
[27] A.Z. Zelikovsky, "A Faster Approximation Algorithm for the Steiner Tree Problem in Graphs," Information Processing Letters, vol. 46, no. 2, pp. 79-83, 1993.
[28] A.Z. Zelikovsky, "An 11/6 Approximation Algorithm for the Network Steiner Problem," Algorithmica, vol. 9, pp. 463-470, 1993.
[29] A.Z. Zelikovsky, P. Berman, and M. Karpinski, "Improved Approximation Bounds for the Rectlinear Steiner Tree Problem," Technical Report No. 85108-CS, Institut für Informatik, Universität Bonn, 1994.

Index Terms:
Steiner trees, exact algorithms, optimization, placement problem, gate level design.
Citation:
Majid Sarrafzadeh, Wei-Liang Lin, C.k. Wong, "Floating Steiner Trees," IEEE Transactions on Computers, vol. 47, no. 2, pp. 197-211, Feb. 1998, doi:10.1109/12.663766
Usage of this product signifies your acceptance of the Terms of Use.