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Efficient Multiplier Architectures for Galois Fields GF(24n)
February 1998 (vol. 47 no. 2)
pp. 162-170
ASCII Text
x 
 
Christof Paar, Peter Fleischmann, Peter Roelse, "Efficient Multiplier Architectures for Galois Fields GF(24n)," IEEE Transactions on Computers, vol. 47, no. 2, pp. 162-170, February, 1998.
 
 
BibTex
x
 
@article{ 10.1109/12.663762,
author = {Christof Paar and Peter Fleischmann and Peter Roelse},
title = {Efficient Multiplier Architectures for Galois Fields GF(24n)},
journal ={IEEE Transactions on Computers},
volume = {47},
number = {2},
issn = {0018-9340},
year = {1998},
pages = {162-170},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.663762},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Efficient Multiplier Architectures for Galois Fields GF(24n)
IS - 2
SN - 0018-9340
SP162
EP170
EPD - 162-170
A1 - Christof Paar,
A1 - Peter Fleischmann,
A1 - Peter Roelse,
PY - 1998
KW - Galois fields
KW - composite fields
KW - multiplication
KW - Karatsuba Ofman
KW - modulo reduction
KW - bit parallel
KW - VLSI architecture.
VL - 47
JA - IEEE Transactions on Computers
ER -
 

Abstract—This contribution introduces a new class of multipliers for finite fields GF((2n)4). The architecture is based on a modified version of the Karatsuba-Ofman algorithm (KOA). By determining optimized field polynomials of degree four, the last stage of the KOA and the modulo reduction can be combined. This saves computation and area in VLSI implementations. The new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with KOA-based architectures with separate modulo reduction. The new multipliers lead to highly modular architectures and are, thus, well suited for VLSI implementations. Three types of field polynomials are introduced and conditions for their existence are established. For the small fields, where n = 2, 3, ..., 8, which are of primary technical interest, optimized field polynomials were determined by an exhaustive search. For each field order, exact space and time complexities are provided.

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Index Terms:
Galois fields, composite fields, multiplication, Karatsuba Ofman, modulo reduction, bit parallel, VLSI architecture.
Citation:
Christof Paar, Peter Fleischmann, Peter Roelse, "Efficient Multiplier Architectures for Galois Fields GF(24n)," IEEE Transactions on Computers, vol. 47, no. 2, pp. 162-170, Feb. 1998, doi:10.1109/12.663762
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