Issue No.02 - February (1998 vol.47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.663762
<p><b>Abstract</b>—This contribution introduces a new class of multipliers for finite fields <it>GF</it>((2<super><it>n</it></super>)<super>4</super>). The architecture is based on a modified version of the Karatsuba-Ofman algorithm (KOA). By determining optimized field polynomials of degree four, the last stage of the KOA and the modulo reduction can be combined. This saves computation and area in VLSI implementations. The new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with KOA-based architectures with separate modulo reduction. The new multipliers lead to highly modular architectures and are, thus, well suited for VLSI implementations. Three types of field polynomials are introduced and conditions for their existence are established. For the small fields, where <it>n</it> = 2, 3, ..., 8, which are of primary technical interest, optimized field polynomials were determined by an exhaustive search. For each field order, exact space and time complexities are provided.</p>
Galois fields, composite fields, multiplication, Karatsuba Ofman, modulo reduction, bit parallel, VLSI architecture.
Christof Paar, Peter Fleischmann, Peter Roelse, "Efficient Multiplier Architectures for Galois Fields GF(24n)", IEEE Transactions on Computers, vol.47, no. 2, pp. 162-170, February 1998, doi:10.1109/12.663762