This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Novel Approach to Random Pattern Testing of Sequential Circuits
January 1998 (vol. 47 no. 1)
pp. 129-134

Abstract—Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modifications are made. In this paper, we propose a novel approach to improve the random pattern testability of sequential circuits. We introduce the concept of holding signals at primary inputs and scan flip-flops of a partially scanned sequential circuit for a certain length of time, instead of applying a new random vector at each clock cycle. When a random vector is held at the primary inputs of the circuit under test or at the scan flip-flops, the system clock is applied and the primary outputs of the circuit are observed. Information obtained from a testability analysis or test generator is used to determine the number of clock cycles for which each random vector is to be held constant. The method is low cost and the results of our experiment on the benchmark circuits show that it is very effective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full scan.

[1] K. Parker, "Adaptive Random Test Generation," J. Design Automation and Fault Tolerant Computing, vol. 1, pp. 62-68, 1976.
[2] F. Saivoshi, WTPGA: A Novel Weighted Test Pattern Generation Approach for VLSI BIST Proc. Int'l Test Conf., pp. 256-262, 1988.
[3] J.A. Waicukauski and E. Lindbloom, Fault Detection Effectiveness of Weighted Random Patterns Proc. Int'l Test Conf., pp. 245-261, 1988.
[4] T. Kelsey, K. Saluja, and S. Lee, "An Efficient Algorithm for Sequential Circuit Test Generation," IEEE Trans. Computers, vol. 42, no. 11, pp. 1,361-1,371, Nov. 1993.
[5] I. Pomeranz and S. Reddy, "The Multiple Observation Time Test Strategy," IEEE Trans. Computers, vol. 41, no. 5, pp. 627-637, May 1992.
[6] T. Niermann and J. Patel, HITEC: A Test Generation Package for Sequential Circuits Proc. European Conf. Design Automation, pp. 214-218, 1991.
[7] W. Cheng and T. Chakraborty, "Gentest—An Automatic Test Generation System for Sequential Circuits," Computer, pp. 43-49, Apr. 1989.
[8] M. Abramovici, M. Breuer, and D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[9] V. Agrawal, K. Cheng, D. Johnson, and T. Lin, "Designing Circuits with Partial Scan," IEEE Design and Test of Computers, pp. 8-15, Apr. 1988.
[10] H. Wunderlich, "The Design of Random-Testable Sequential Circuits," Proc. Int'l Symp. Fault-Tolerant Computing, pp. 110-117, June 1989.
[11] M. Abramovici, K. Rajan, and D. Miller, "FREEZE: A New Approach for Testing Sequential Circuits," Proc. European Conf. Design Automation, pp. 22-25, 1992.
[12] P. Bardell and J. Savir, "Test and Diagnosis of Associated Output Logic for Products Having Embedded Arrays," U.S. Patent No. 5442640, Aug. 1995.
[13] L. Nachman, K.K. Saluja, S. Upadhyaya, and R. Reuse, “Random Pattern Testing for Sequential Circuits Revisited,” Proc. 26th Fault-Tolerant Computing Symp., pp. 44-52, June 1996.
[14] K. Kim and C. Kime, "Partial Scan Using Reverse Direction Empirical Testability," Proc. Int'l Test Conf., pp. 498-506, 1993.
[15] K.-T. Cheng and V. Agrawal, "An Economical Scan Design for Sequential Logic Test Generation," Proc. Int'l Symp. Fault-Tolerant Computing, pp. 28-35, 1989.
[16] L.H. Goldstein and E.L. Thigpen, "SCOAP: Sandia Controllability/Observability Analysis Program," Proc. Design Automation Conf., pp. 190-196, 1980.
[17] K. Cheng and V. Agrawal, "Concurrent Test Generation and Design for Testability," Proc. Int'l Symp. Computer Automated Systems, pp. 1,935-1,938, 1989.
[18] N. Gouders and R. Kaibel, "Advanced Techniques for Sequential Test Generation," Proc. European Test Conf., pp. 293-300, 1991.
[19] D. Lee and S.M. Reddy, "A New Test Generation Method for Sequential Circuits," Digest Int'l Conf. Computer-Aided Design, pp. 446-449, 1991.
[20] B. So, "Time Efficient Automatic Test Pattern Generation Systems," PhD thesis, Dept. of Electrical and Computer Eng., Univ. of Wisconsin-Madison, 1994.
[21] P. Maxwell and R. Aitken, "All Fault Coverages Are Not Created Equal," IEEE Design and Test of Computers, vol. 10, pp. 42-51, Mar. 1993.
[22] F. Muradali, T. Nishida, and T. Shimizu, "A Structure and Technique for Pseudorandom-Based Testing of Sequential Circuits," J. Electronic Testing: Theory and Application, vol. 6, pp. 107-115, 1995.

Index Terms:
Fault coverage, hold method, partial scan, random pattern testing, sequential circuit testing.
Citation:
Lama Nachman, Kewal K. Saluja, S.j. Upadhyaya, Robert Reuse, "A Novel Approach to Random Pattern Testing of Sequential Circuits," IEEE Transactions on Computers, vol. 47, no. 1, pp. 129-134, Jan. 1998, doi:10.1109/12.656097
Usage of this product signifies your acceptance of the Terms of Use.