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A Dependable High Performance Wafer Scale Architecture for Embedded Signal Processing
January 1998 (vol. 47 no. 1)
pp. 125-128

Abstract—A high performance, programmable, floating point multiprocessor architecture has been specifically designed to exploit advanced two- and three-dimensional hybrid wafer scale packaging to achieve low size, weight, and power, and improve reliability for embedded systems applications. Processing elements comprised of a 0.8 micron CMOS dual processor chip and commercial synchronous SRAMs achieve more than 100 MFLOPS/Watt. This power efficiency allows up to 32 processing elements to be incorporated into a single 3D multichip module, eliminating multiple discrete packages and thousands of wirebonds. The dual processor chip can dynamically switch between independent processing, watchdog checking, and coprocessing modes. A flat, SRAM memory provides predictable instruction set timing and independent and accurate performance prediction.

[1] R.A. Filion, R.J. Wojnarowski, T.B. Gorcyzca, E.J. Wildi, and H.S. Cole, "Development of a Plastic Encapsulated Multichip Technology for High Volume, Low Cost Commercial Electronics," IEEE Trans. Components, Packaging, and Manufacturing Technology Part B: Advanced Packaging, vol. 18, no. 1, pp. 59-65, Feb. 1995.
[2] PCI Special Interest Group, "PCI Local Bus Specification, Revision 2.1,"Portland, Ore., 1995.
[3] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, Calif., 1990.
[4] R.W. Linderman, "Density Improvement for Planar Hybrid Wafer Scale Integration," U.S. Patent 5,432,681, July11, 1995.
[5] J.M. Kallis and M.D. Norris, "Effect of Steady-State Operating Temperature on Power Cycling Durability of Electronic Assemblies," Proc. 12th Biennial Conf. Reliability, Stress Analysis, and Failure Prevention, Apr.15-17, 1997.
[6] U. Dayal, N. Goodman, and R.H. Katz, “An Extended Relational Algebra with Control over Duplicate Elimination,” Proc. ACM Symp. Principles of Database Systems, pp. 117–123, 1982.
[7] Fault Tolerant Computing, D.K. Pradhan, ed., pp. 455-460. Prentice Hall, 1996.
[8] ANSI/IEEE Std 896.1-1994, FutureBus+ Logical Protocol Specification.
[9] J.A. Minahan et al., "The 3D Stack in Short Form," Proc. ECTC, pp. 340-344, 1992.
[10] M.W. Yung and M.J. Little, "A New Approach to Implement a Defect Tolerant Power Distribution Network in WSI Circuit," Proc. 1991 Int'l Conf. Wafer Scale Integration, pp. 215-222, Jan. 1991.
[11] M.W. Yung and M.J. Little, "A New Approach to Implement a Defect Tolerant Power Distribution Network in WSI Circuit," Proc. 1991 Int'l Conf. Wafer Scale Integration, pp. 215-222, Jan. 1991.
[12] C.M. Maunder and R.E. Tulloss, The Test Access Port and Boundary-Scan Architecture. IEEE CS Press, 1990.
[13] A. Vaidyanath, B. Thoroddsen, and J.L. Prince, "Effect of CMOS Driver Loading Conditions on Simultaneous Switching Noise," IEEE Trans. Components, Packaging, and Manufacturing Technology, Part B, vol. 17, no. 4, pp. 480-485, Nov. 1994.

Index Terms:
Computer reliability, embedded processing, wafer scale integration, parallel architectures, memory hierarchies, high-speed integrated circuits.
Citation:
Richard W. Linderman, Ralph L.R. Kohler, Mark H. Linderman, "A Dependable High Performance Wafer Scale Architecture for Embedded Signal Processing," IEEE Transactions on Computers, vol. 47, no. 1, pp. 125-128, Jan. 1998, doi:10.1109/12.656096
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