Issue No.01 - January (1998 vol.47)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.656096
<p><b>Abstract</b>—A high performance, programmable, floating point multiprocessor architecture has been specifically designed to exploit advanced two- and three-dimensional hybrid wafer scale packaging to achieve low size, weight, and power, and improve reliability for embedded systems applications. Processing elements comprised of a 0.8 micron CMOS dual processor chip and commercial synchronous SRAMs achieve more than 100 MFLOPS/Watt. This power efficiency allows up to 32 processing elements to be incorporated into a single 3D multichip module, eliminating multiple discrete packages and thousands of wirebonds. The dual processor chip can dynamically switch between independent processing, watchdog checking, and coprocessing modes. A flat, SRAM memory provides predictable instruction set timing and independent and accurate performance prediction.</p>
Computer reliability, embedded processing, wafer scale integration, parallel architectures, memory hierarchies, high-speed integrated circuits.
Richard W. Linderman, Ralph L.R. Kohler, Mark H. Linderman, "A Dependable High Performance Wafer Scale Architecture for Embedded Signal Processing", IEEE Transactions on Computers, vol.47, no. 1, pp. 125-128, January 1998, doi:10.1109/12.656096