This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Abstraction Techniques for Validation Coverage Analysis and Test Generation
January 1998 (vol. 47 no. 1)
pp. 2-14

Abstract—The enormous state spaces which must be searched when verifying the correctness of, or generating tests for, complex circuits precludes the use of traditional approaches. Hard-to-find abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. This control flow, capturing the essential "behavior" of the circuit, is represented as a finite state machine called the ECFM (Extracted Control Flow Machine).

Simulation is currently the primary means of verifying large circuits, but the definition of a coverage measure for simulation vectors is an open problem. We define functional coverage as the amount of control behavior covered by the test suite. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph. We also demonstrate how the same abstraction techniques can complement ATPG techniques when attacking hard-to-detect faults in the control part of the design for which conventional ATPG alone proves to be inadequate or inefficient at best. Results on large designs show significant improvement over conventional algorithms.

[1] L.A. Clarke and D.J. Richardson, “Applications of Symbolic Evaluation,” J. Systems and Software, vol. 5, no. 1, pp. 15–35, 1985.
[2] M. Abadir and H. Reghbati, "Functional Specification and Testing of Logic Circuits," Computers and Math. with Applications, vol. 11, no. 12, pp. 1,143-1,153, 1985.
[3] R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp. 667-690.
[4] J. Burch, E. Clarke, K. McMillan, and D. Dill, "Sequential Circuit Verification Using Symbolic Model Checking," Proc. 27th Design Automation Conf., pp. 46-51, 1990.
[5] K. Cheng and J. Jou, "A Functional Fault Model to Sequential Machines," IEEE Trans. Computer-Aided Design, vol. 11, no. 9, pp. 1,065-1,073, 1992.
[6] K. Cheng and A. Krishnakumar, "Automatic Functional Test Generation Using the Extended Finite State Machine Model," Proc. 30th Design Automation Conf., pp. 86-91, 1993.
[7] H. Cho, G. Hachtel, and F. Somenzi, "Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration," IEEE Trans. Computer-Aided Design, vol. 12, no. 7, pp. 935-945, 1993.
[8] P. Chung, Y. Wang, and I. Hajj, "Diagnosis and Correction of Logic Design Errors in Digital Circuits," Proc. 30th Design Automation Conf., pp. 503-508, 1993.
[9] O. Coudert, C. Berthet, and J. Madre, "Verification of Sequential Machines Using Boolean Functional Vectors," Formal VLSI Correctness Verification, pp. 179-196. Elsevier Science, 1990.
[10] W. Cullyer, "Implementing Safety-Critical Systems: The Viper Microprocessor," VLSI Specification, Verification and Synthesis, G. Virtwistle and P. Subrahmanyam, eds., pp. 1-26. Kluwer Academic, 1988.
[11] D. Geist, M. Farkas, A. Landver, Y. Lichtenstein, S. Ur, and Y. Wolfsthal, "Coverage-Directed Test Generation Using Symbolic Techniques," Proc. Formal Methods in Computer-Aided Design, 1996.
[12] R. Ho, C. Yang, M. Horowitz, and D. Dill, "Architecture Validation for Processors," Proc. 22nd Int'l Symp Computer Architecture, pp. 404-413, 1995.
[13] Y.V. Hoskote, D. Moundanos, and J.A. Abraham, "Automatic Extraction of the Control Flow Machine and Application to Evaluating Coverage of Verification Vectors," Proc. Int'l Conf. Computer Design, pp. 532-537, 1995.
[14] S.-Y. Huang, K.-T. Cheng, and K.-C. Chen, "AQUILA: An Equivalence Verifier for Large Sequential Circuits," Proc. Asia-Pacific Design Automation Conf., 1997.
[15] S. Kang and S. Szygenda, "Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling," IEEE Design and Test of Computers, pp. 18-26, 1994.
[16] J. Moondanos and J.A. Abraham, "Sequential Redundancy Identification Using Verification Techniques," Proc. Int'l Test Conf., pp. 197-205, 1992.
[17] D. Moundanos, J.A. Abraham, and Y.V. Hoskote, "A Unified Framework for Design Validation and Manifacturing Test," Proc. IEEE Int'l Test Conf., IEEE Computer Soc. Press, Los Alamitos, Calif., 1996, pp. 875-884.
[18] T. Niermann and J. Patel, HITEC: A Test Generation Package for Sequential Circuits Proc. European Conf. Design Automation, pp. 214-218, 1991.
[19] T. Shintani and M. Kitsuregawa, Parallel Mining Algorithms for Generalized Association Rules With Classification Proc. 1998 ACM SIGMOD Int'l Conf. Management of Data, pp. 25-36, 1998.
[20] H. Touati, H. Savoj, B. Lin, R. Brayton, and A. Sangiovanni-Vincentelli, "Implicit State Enumeration of Finite State Machines Using BDDs," Proc. Int'l Conf. Computer-Aided Design, pp. 130-133, 1990.

Index Terms:
OBDDs, testing, stuck-at-fault model, verification, abstraction, extracted control flow machine, coverage analysis.
Citation:
Dinos Moundanos, Jacob A. Abraham, Yatin V. Hoskote, "Abstraction Techniques for Validation Coverage Analysis and Test Generation," IEEE Transactions on Computers, vol. 47, no. 1, pp. 2-14, Jan. 1998, doi:10.1109/12.656068
Usage of this product signifies your acceptance of the Terms of Use.