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A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems
December 1997 (vol. 46 no. 12)
pp. 1387-1395
ASCII Text
x 
 
Suresh Chalasani, "A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems," IEEE Transactions on Computers, vol. 46, no. 12, pp. 1387-1395, December, 1997.
 
 
BibTex
x
 
@article{ 10.1109/12.641940,
author = {Suresh Chalasani},
title = {A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems},
journal ={IEEE Transactions on Computers},
volume = {46},
number = {12},
issn = {0018-9340},
year = {1997},
pages = {1387-1395},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.641940},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems
IS - 12
SN - 0018-9340
SP1387
EP1395
EPD - 1387-1395
A1 - Suresh Chalasani,
PY - 1997
KW - Hierarchical switching systems
KW - time-slot assignment
KW - Clos networks
KW - permutation networks
KW - routing algorithms.
VL - 46
JA - IEEE Transactions on Computers
ER -
 

Abstract—The time-slot assignment (TSA) problem in a TDM switching system is to find a conflict-free assignment of traffic-units to slots such that the frame-length is minimized. In this paper, we develop a new parallel algorithm for the TSA problem in hierarchical switching systems (HSS). To design the parallel algorithm, we first reduce the TSA problem to the problem of routing permutations in three-stage Clos networks; we also show how this reduction can be achieved in polylogarithmic time using a polynomial number of processors on the EREW PRAM model. Once this reduction is achieved, we use existing parallel algorithms in literature to route permutations in Clos networks. The overall time-complexity of our parallel algorithm is O(log3X) using O(MX) processors, where X = max{M, L}, M is the number of inputs of the HSS, and L is the length of the time-slot assignment. This result is a significant improvement upon the earlier parallel algorithms, which require O(M2 log M log L) time and O(ML) processors to solve the TSA problem.

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Index Terms:
Hierarchical switching systems, time-slot assignment, Clos networks, permutation networks, routing algorithms.
Citation:
Suresh Chalasani, "A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems," IEEE Transactions on Computers, vol. 46, no. 12, pp. 1387-1395, Dec. 1997, doi:10.1109/12.641940
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