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| Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng, "A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors," IEEE Transactions on Computers, vol. 46, no. 12, pp. 1363-1371, December, 1997. | |||
| BibTex | x | ||
| @article{ 10.1109/12.641936, author = {Yung-Yuan Chen and Shambhu J. Upadhyaya and Ching-Hwa Cheng}, title = {A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors}, journal ={IEEE Transactions on Computers}, volume = {46}, number = {12}, issn = {0018-9340}, year = {1997}, pages = {1363-1371}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.641936}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors IS - 12 SN - 0018-9340 SP1363 EP1371 EPD - 1363-1371 A1 - Yung-Yuan Chen, A1 - Shambhu J. Upadhyaya, A1 - Ching-Hwa Cheng, PY - 1997 KW - VLSI/WSI array processor KW - performance analysis KW - reconfiguration process KW - redundancy scheme KW - switch programming KW - yield simulation. VL - 46 JA - IEEE Transactions on Computers ER - | |||
Abstract—This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switching network failures. This yield simulation tool can also be used to obtain the information on the performance degradation, spare replacement, processor placement, routing and the switch programming algorithm survival probability.
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