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A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
December 1997 (vol. 46 no. 12)
pp. 1363-1371

Abstract—This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switching network failures. This yield simulation tool can also be used to obtain the information on the performance degradation, spare replacement, processor placement, routing and the switch programming algorithm survival probability.

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Index Terms:
VLSI/WSI array processor, performance analysis, reconfiguration process, redundancy scheme, switch programming, yield simulation.
Citation:
Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng, "A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors," IEEE Transactions on Computers, vol. 46, no. 12, pp. 1363-1371, Dec. 1997, doi:10.1109/12.641936
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