Publication 1997 Issue No. 10 - October Abstract - Signed-Digit Architecture for Residue to Binary Transformation
Signed-Digit Architecture for Residue to Binary Transformation
October 1997 (vol. 46 no. 10)
pp. 1146-1150
 ASCII Text x F. Pourbigharaz, H.m. Yassine, "Signed-Digit Architecture for Residue to Binary Transformation," IEEE Transactions on Computers, vol. 46, no. 10, pp. 1146-1150, October, 1997.
 BibTex x @article{ 10.1109/12.628400,author = {F. Pourbigharaz and H.m. Yassine},title = {Signed-Digit Architecture for Residue to Binary Transformation},journal ={IEEE Transactions on Computers},volume = {46},number = {10},issn = {0018-9340},year = {1997},pages = {1146-1150},doi = {http://doi.ieeecomputersociety.org/10.1109/12.628400},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - Signed-Digit Architecture for Residue to Binary TransformationIS - 10SN - 0018-9340SP1146EP1150EPD - 1146-1150A1 - F. Pourbigharaz, A1 - H.m. Yassine, PY - 1997KW - VLSI arithmetic algorithmsKW - residue number systemsKW - residue to binary conversionKW - signed-digit number systemsKW - Chinese remainder theoremKW - digital signal processing.VL - 46JA - IEEE Transactions on ComputersER -

Abstract—A residue to binary converter architecture based on the Chinese Remainder Theorem (CRT) is presented. This is achieved by introducing a general moduli set Sk

$$S^k=\left\{ {2^m-1,\,\,2^{2^0m}+1,\,\,2^{2^1m}+1,\,\,2^{2^2m}+1,\,\,\ldots ,\, \,2^{2^km}+1} \right\}$$for Residue Number System (RNS) applications. Residue to binary converter architectures based on moduli sets S0 = {2m− 1, 2m + 1} and S1 = {2m− 1, 2m + 1, 22m + 1} are developed. The conversion procedure is performed in the following three levels:

•   residue to signed-digit,•   signed-digit to binary,•   end-around carry addition/subtraction.

In the first level of operation, the signed-digit representation of the CRT equation is realized by using redundant adder/subtractor blocks. Here, the necessary embedded multiplications are replaced by simple shift-left operations and the carry propagation is totally eliminated. In the second level, the redundant representation of CRT is directly converted to binary format. Finally, an end-around carry (EAC) addition/subtraction is performed to obtain the result at the third level of operation. The proposed architectures are simple, fast, free of memory blocks and modulo adders.

[1] A. Avizienis, "Signed-Digit Number Representation for Fast Parallel Arithmetic," IRE Trans. Electronic Computers, vol. 10, pp. 389-400, Sept. 1961.
[2] H.L. Garner, "The Residue Number System," IRE Trans. Electronic Computers, vol. 8, pp. 140-147, June 1959.
[3] N. Szabo and R. Tanaka, Residue Arithmetic and its Application to Computer Technology.New York: McGraw-Hill, 1967.
[4] M.A. Soderstrand,W.K. Jenkins,G.A. Jullien,, and F.J. Taylor,Residue Number System Arithmetic: Modern Applicationsin Digital Signal Processing. IEEE Press, 1986.
[5] S.J. Piestrak, "Design of Residue Generators and Multi-Operand Modular Adders Using Carry-Save Adders," Proc. 10th IEEE Symp. Computer Arithmetic, pp. 100-107, June 1991.
[6] F. Pourbigharaz and H.M. Yassine, "Simple Binary to Residue Transformation with Respect to 2m+ 1 Moduli," IEE Proc. Circuits, Devices, and Systems, Part G, vol. 141, no. 6, pp. 522-526, Dec. 1994.
[7] V. Piuri, M. Berzieri, A. Bisaschi, and A. Fabi, "Residue Arithmetic for a Fault-Tolerant Multiplier: The Choice of the Best Triple of Bases," Microprocessors and Microprogramming, vol. 20, pp. 15-23, 1988.
[8] F. Pourbigharaz and H.M. Yassine, "Modulo-Free Architecture for Binary to Residue Transformations with Respect to {2m- 1, 2m, 2m+ 1} Moduli Set," Proc. IEEE Int'l Symp. Circuits and Systems, vol. 2, pp. 317-320,London, May 1994.
[9] K. Elleithy and M. Bayoumi, “Fast and Flexible Architectures for RNS Arithmetic Decoding,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, pp. 226-235, Apr. 1992.
[10] K.M. Ibrahim and S.N. Saloum, “An Efficent Residue to Binary Converter Design,” IEEE Trans. Circuits and Systems, vol. 35, no. 9, pp. 1,156-1,158, Sept. 1988.
[11] A.S. Shenoy and R. Kumaresan, "Residue to Binary Conversion for RNS Arithmetic Using Only Modular Look-Up Tables," IEEE Trans. Circuits and Systems, vol. 35, no. 9, pp. 1,158-1,162, Sept. 1988.
[12] S. Andraos and H. Ahmad, “A New Efficient Memoryless Residue to Binary Converter,” IEEE Trans. Circuits and Systems, vol. 35, no. 11, pp. 1.441-1,444, Nov. 1988.
[13] P.V. Ananda Mohan and D.V. Poornaiah, "Novel RNS to Binary Converters," IEEE Int'l Symp. Circuits and Systems,Singapore, June 1991.
[14] F. Pourbigharaz and H.M. Yassine, "Intermediate Signed-Digit Stage to Perform Residue to Binary Transformations Based on CRT," Proc. IEEE Int'l Symp. Circuits and Systems, vol. 2, pp. 353-356,London, May 1994.
[15] T. Stouraitis, "Efficient Convertors for Residue and Quadratic-Residue Number Systems," IEE Proc. Circuits, Devices, and Systems, Part G, vol. 139, no. 6, Dec. 1992.

Index Terms:
VLSI arithmetic algorithms, residue number systems, residue to binary conversion, signed-digit number systems, Chinese remainder theorem, digital signal processing.
Citation:
F. Pourbigharaz, H.m. Yassine, "Signed-Digit Architecture for Residue to Binary Transformation," IEEE Transactions on Computers, vol. 46, no. 10, pp. 1146-1150, Oct. 1997, doi:10.1109/12.628400