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Issue No.10 - October (1997 vol.46)
pp: 1142-1145
ABSTRACT
<p><b>Abstract</b>—<it>Branch target buffers</it>, or BTBs, are small caches for program branching information. Like data caches, addresses are divided into equivalence classes based on their low order bits. Unlike data caches, however, complete resolution of a single address from within an equivalence class is not required for correct execution. Substantial savings are therefore possible by employing <it>partial resolution</it>, using fewer tag bits than necessary to uniquely identify an address. We present the relationship between the number of tag bits in a branch target buffer and prediction accuracy, based on dynamic simulations of the SPECINT92 benchmark suite. For a 512 entry BTB, on average only two tag bits are necessary to obtain 99.9 percent of the accuracy obtainable with a full tag; no more than nine tag bits are required to obtain identical prediction accuracy. This suggests that microprocessors can achieve substantial area savings in their BTB tag stores by employing partial resolution.</p>
INDEX TERMS
Branch prediction, branch target buffer, cache memory, computer architecture, microarchitecture.
CITATION
Barry Fagin, "Partial Resolution in Branch Target Buffers", IEEE Transactions on Computers, vol.46, no. 10, pp. 1142-1145, October 1997, doi:10.1109/12.628399
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