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The Reconfigurable Ring of Processors: Fine-Grain Tree-Structured Computations
October 1997 (vol. 46 no. 10)
pp. 1119-1131

Abstract—We study fine-grain computation on the Reconfigurable Ring of Processors $({\cal RRP}),$ a parallel architecture whose processing elements (PEs) are interconnected via a multiline reconfigurable bus, each of whose lines has one-packet width and can be configured, independently of other lines, to establish an arbitrary PE-to-PE connection. We present a "cooperative" message-passing protocol that will, in the presence of suitable implementation technology, endow an ${\cal RRP}$ with message latency that is logarithmic in the number of PEs a message passes over in transit. Our study focuses on the computational consequences of such latency in such an architecture. Our main results prove that: 1) an N-PE ${\cal RRP}$ can execute a sweep up or down an N-leaf complete binary tree in time proportional to log N log log N; 2) a broad range of N-PE architectures, including N-PE ${\cal RRP}{\rm s},$ require time proportional to log N log log N to perform such a sweep.

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Index Terms:
Communication protocols, dynamically reconfigurable parallel architectures, fine-grain parallel computing, rings of processors, tree-sweep algorithms.
Citation:
Arnold L. Rosenberg, Vittorio Scarano, Ramesh K. Sitaraman, "The Reconfigurable Ring of Processors: Fine-Grain Tree-Structured Computations," IEEE Transactions on Computers, vol. 46, no. 10, pp. 1119-1131, Oct. 1997, doi:10.1109/12.628396
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