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Antonio Fernández, Kemal Efe, "Efficient VLSI Layouts for Homogeneous Product Networks," IEEE Transactions on Computers, vol. 46, no. 10, pp. 10701082, October, 1997.  
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@article{ 10.1109/12.628392, author = {Antonio Fernández and Kemal Efe}, title = {Efficient VLSI Layouts for Homogeneous Product Networks}, journal ={IEEE Transactions on Computers}, volume = {46}, number = {10}, issn = {00189340}, year = {1997}, pages = {10701082}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.628392}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Efficient VLSI Layouts for Homogeneous Product Networks IS  10 SN  00189340 SP1070 EP1082 EPD  10701082 A1  Antonio Fernández, A1  Kemal Efe, PY  1997 KW  Interconnection networks KW  product networks KW  VLSI KW  collinear layout KW  separator KW  bifurcator. VL  46 JA  IEEE Transactions on Computers ER   
Abstract—In this paper, we develop generalized methods to layout homogeneous product networks with any number of dimensions, and analyze their VLSI complexity by deriving upper and lower bounds on the area and maximum wire length.
In the literature, lower bounds are generally obtained by computing lower bounds on the bisection width or the crossing number of the network being laid out. In this paper, we define a new measure that we call "maximal congestion," that can be used to obtain both the bisection width and the crossing number, thereby unifying the two approaches. Upper bounds are traditionally obtained by constructing layouts based on separators or bifurcators. Both methods have the basic limitation that they are applicable only for graphs with bounded vertex degree. The separators approach generally yields good layouts when good separators can be found, but it is difficult to find a good separator for an arbitrary graph. The bifurcators approach is easier to apply, but it generally yields larger area and wire lengths. We show how to obtain "strong separators" as well as bifurcators for any homogeneous product network, as long as the factor graph has bounded vertex degree. We illustrate application of both methods to layout a number of interesting product networks.
Furthermore, we introduce a new layout method for product networks based on the combination of collinear layouts. This method is more powerful than the two methods above because it is applicable even when the factor graph has unbounded vertex degree. It also yields smaller area than the earlier methods. In fact, our method has led to the optimal area for all of the homogeneous product networks we considered in this paper with one exception, which is very close to optimal. In regards to wire lengths, the results obtained by our method turned out to be the best of the three methods for all the examples we considered, again subject to one (and the same) exception. We give an extensive variety of such examples.
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