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Design Principles for Practical Self-Routing Nonblocking Switching Networks with O(N · log N) Bit-Complexity
October 1997 (vol. 46 no. 10)
pp. 1057-1069

Abstract—Principles for designing practical self-routing nonblocking N×N circuit-switched connection networks with optimal θ(N· log N) hardware at the bit-level of complexity are described. The overall principles behind the architecture can be described as "Expand-Route-Contract." A self-routing nonblocking network with w-bit wide datapaths can be achieved by expanding the datapaths to w + z independent bit-serial connections, routing these connections through self-routing networks with blocking, and by contracting the data at the output and recovering the w-bit wide datapaths. For an appropriate redundancy z, the blocking probability can be made arbitrarily small and the fault tolerance arbitrarily high. By using efficient space domain concentrators, the architecture yields self-routing nonblocking switching networks with an optimal O(N· log N) bits of memory or O(N· log N· log log log N) logic gates. By using a linear-cost time domain concentrator, the architecture yields self-routing nonblocking switching networks with an optimal θ(N· log N) bits of memory or logic gates. These designs meet Shannon's lower bound on memory requirements, established in the 1950s. The number of stages of crossbars can match the theoretical minimum, which has not been achieved by previous self-routing networks. The architecture is feasible with existing electrical or optical technologies. The designs of electrical and optical switch cores with Terabits of bisection bandwidth for Networks-of-Workstations (NOWs) are described.

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Index Terms:
Multistage, networks, self-routing, nonblocking, circuit-switching, scalable, randomization, electrical, optical.
Ted H. Szymanski, "Design Principles for Practical Self-Routing Nonblocking Switching Networks with O(N · log N) Bit-Complexity," IEEE Transactions on Computers, vol. 46, no. 10, pp. 1057-1069, Oct. 1997, doi:10.1109/12.628391
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