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High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm
August 1997 (vol. 46 no. 8)
pp. 855-870

Abstract—Traditionally, CORDIC algorithms have employed radix-2 in the first n/2 microrotations (n is the precision in bits) in order to preserve a constant scale factor. In this work, we will present a full radix-4 CORDIC algorithm in rotation mode and circular coordinates and its corresponding selection function, and we will propose an efficient technique for the compensation of the nonconstant scale factor. Three radix-4 CORDIC architectures are implemented: 1) a word serial architecture based on the zero skipping technique, 2) a pipelined architecture, and 3) an application specific architecture (the angles are known beforehand). The first two are general purpose implementations where redundant (carry-save) or nonredundant arithmetic can be used, whereas the last one is a simplification of the first two. The proposed architectures present a good trade-off between latency and hardware complexity when compared with already existing CORDIC architectures.

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Index Terms:
CORDIC algorithm, radix-4, redundant arithmetic, VLSI architectures, pipelined architectures.
Citation:
Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata, "High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm," IEEE Transactions on Computers, vol. 46, no. 8, pp. 855-870, Aug. 1997, doi:10.1109/12.609275
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