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Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches
May 1997 (vol. 46 no. 5)
pp. 603-610

Abstract—Although direct-mapped caches suffer from higher miss ratios as compared to set-associative caches, they are attractive for today's high-speed pipelined processors that require very low access times. Victim caching was proposed by Jouppi [1] as an approach to improve the miss rate of direct-mapped caches without affecting their access time. This approach augments the direct-mapped main cache with a small fully-associate cache, called victim cache, that stores cache blocks evicted from the main cache as a result of replacements. We propose and evaluate an improvement of this scheme, called selective victim caching. In this scheme, incoming blocks into the first-level cache are placed selectively in the main cache or a small victim cache by the use of a prediction scheme based on their past history of use. In addition, interchanges of blocks between the main cache and the victim cache are also performed selectively.

We show that the scheme results in significant improvements in miss rate as well as the average memory access time, for both small and large caches (4 Kbytes-128 Kbytes). For example, simulations with ten instruction traces from the SPEC '92 benchmark suite showed an average improvement of approximately 21percent in miss rate over simple victim caching for a 16-Kbyte cache with a block size of 32 bytes; the number of blocks interchanged between the main and victim caches reduced by approximately 70 percent. Implementation alternatives for the scheme in an on-chip processor cache are also described.

[1] N.P. Jouppi, “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers,” Proc. 17th Int'l Symp. Computer Architecture, pp. 364-373, May 1990.
[2] B. Prince, Semiconductor Memories. Wiley Publishers, 1991.
[3] A.J. Smith, "Cache Memories," ACM Computing Surveys, Vol. 14, 1982, pp. 473-540.
[4] M.D. Hill, "A Case for Direct-Mapped Caches," Computer, pp. 25-40, Dec. 1988.
[5] S. Przybylski, M. Howrowitz, and J. Hennessy, "Performance Tradeoffs in Cache Design," Proc. 15th Int'l Symp. Computer Architecture, pp. 290-298, June 1988.
[6] N.P. Jouppi, "Cache Write Policies and Performance," Proc. 20th Ann. Int'l Symp. Computer Architecture, pp. 191-201, May 1993.
[7] S. McFarling, ``Cache Replacement with Dynamic Exclusion,'' Proc. 19th ISCA, pp. 191-200, May 1992.
[8] A. Agarwal and S.D. Pudar, "Column-Associative Caches: a Technique for Reducing the Miss Rate of Direct-Mapped Caches," Proc. 20th Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 1993, pp. 179-190.
[9] E. McLellan, "The Alpha AXP Architecture and 21064 Processor," IEEE Micro, vol. 13, no. 3, pp. 36-47, June 1993.
[10] T. Wada, S. Rajan, and S.A. Przybylski, An Analytical Access Time Model for On-Chip Cache Memories IEEE J. Solid-State Circuits, vol. 27, no. 8, pp. 1147-1156, Aug. 1992.
[11] N. Jouppi and S. Wilton, ``Tradeoffs in Two-Level On-Chip Caching,'' Proc. 21st ISCA, pp. 34-45, Apr. 1994.
[12] S. Wilton and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," Research Report 93/5, Digital Equipment Corp., Western Research Laboratory, 1994.
[13] D. Wall, A. Borg, and R. Kessler, "Generation and Analysis of Very Long Address Traces," Proc. 17th Int'l Symp. Computer Architecture, pp. 290-298, June 1990.
[14] T. Ball and J. Larus, "Optimally Profiling and Tracing Programs," Conf. Record 19th Ann. ACM SIGPLAN-SIGACT Symp. Principles of Programming Languages, Jan. 1992.
[15] J. Flanagan, "A New Methodology for Accurate Trace Collection and Its Application to Memory Hierarchy Performance Modeling," PhD thesis, Brigham Young Univ., Dec. 1993.
[16] K. Grimsrud, J. Archibald, M. Ripley, and K. Flanagan, "BACH: A Hardware Monitor for Tracing Microprocessor-Based Systems," Microprocessors and Microsystems, vol. 17, pp. 443-459, Oct. 1993.
[17] D. Stiliadis and A. Varma, "Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches," Tech. Rep. UCSC-CRL-93-41, U.C. Santa Cruz, 1993 (

Index Terms:
Victim cache, direct-mapped cache, instruction cache, data cache, cache simulation.
Dimitrios Stiliadis, Anujan Varma, "Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches," IEEE Transactions on Computers, vol. 46, no. 5, pp. 603-610, May 1997, doi:10.1109/12.589235
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