Issue No.04 - April (1997 vol.46)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.588058
<p><b>Abstract</b>—A multiprocessor system is fault-tolerant (FT) if it preserves a fault-free subsystem of a predetermined interconnection structure when faults appear. We present a new method for designing FT multiprocessors that can efficiently tolerate both processor and interconnection faults. The approach is general, in that it can be applied to any multiprocessor topology. Shared buses serve as the main interconnection mechanism to minimize the switching logic needed for reconfiguration. We employ processor-bus-link (PBL) graphs to model multiprocessors with either dedicated or shared buses. Both processors and buses are represented as nodes so that bus faults can be considered explicitly and tolerated efficiently by spare buses instead of by spare processors. A minimum number of spare processors and buses are used to reduce hardware overhead. The node covering concept and the maximum-weight spanning tree algorithm are then employed to construct FT systems that have lower interconnection cost than most previous designs. We also present a cost-effective implementation method which is suitable for both static and dynamic reconfiguration techniques. The FT systems obtained have the advantages of no critical single point of failure, low redundancy, local replacement, and simple circuitry for fast reconfiguration.</p>
Fault tolerance, graph model, interconnection method, multiple-bus architecture, point-to-point connection, VLSI design.
Hung-Kuei Ku, John P. Hayes, "Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses", IEEE Transactions on Computers, vol.46, no. 4, pp. 439-455, April 1997, doi:10.1109/12.588058