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Parallel Signature Analysis Design with Bounds on Aliasing
April 1997 (vol. 46 no. 4)
pp. 425-438

Abstract—This paper presents parallel signature design techniques that guarantee the aliasing probability to be less than 2/L, where L is the test length. Using y signature samples, a parallel signature analysis design is proposed that guarantees the aliasing probability to be less than (y/L)y/2. Inaccuracies and incompleteness in previously published bounds on the aliasing probability are discussed. Simple bounds on the aliasing probability are derived for parallel signature designs using primitive polynomials.

[1] E.R. Berlekamp, Algebraic Coding Theory, revised edition. Aegean Park Press, 1984.
[2] S.Z. Hassan, D.J. Lu, and E.J. McCluskey, "Parallel Signature Analyzers—Detection Capability and Extensions," Proc. 26th IEEE CS Int'l Conf., COMPCON, Spring 1983, pp. 440-445, Feb. 1983.
[3] R. David, "Signature Analysis of Multi-Output Circuits," Digest of Papers 14th Ann. Int'l Symp. Fault-Tolerant Computing, pp. 366-371, June 1984.
[4] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[5] M. Damiani et al., "An Analytical Model for the Aliasing Probability in Signature Analysis Testing," IEEE Trans. Computer-Aided Design, vol. 8, no. 11, pp. 1,133-1,144, Nov. 1989.
[6] M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness.New York: W.H. Freeman, 1979.
[7] P. Gelsinger et al., "Computer Aided Design and Built-In Self-Test on the i486TM CPU," Proc. ICCD, pp. 199-201, Oct. 1989.
[8] A. Ivanov. and V.K. Agarwal, "An Analysis of the Probabilistic Behavior of Linear Feedback Signature Registers," IEEE Trans. Computer-Aided Design, vol. 8, no. 10, pp. 1,074-1,088, Oct. 1989.
[9] J. Savir et al., "Random Pattern Testability," IEEE Trans. Computers, vol. 33, no. 1, pp. 79-90, Jan. 1984.
[10] K. Iwasaki and N. Yamaguchi, "Design of Signature Circuits Based on Weight Distribution of Error-Correcting Codes," Proc. ITC, pp. 779-785, Sept. 1990.
[11] E.J. McCluskey et al., "Probability Models for Pseudorandom Test Sequences," IEEE Trans. Computer-Aided Design, vol. 7, no. 1, pp. 68-74, Jan. 1988.
[12] I.M. Ratiu and H.B. Bakoglu, "Pseudorandom Built-In Self-Test Methodology and Implementation for the IBM RISC System/6000 Processor," IBM J. Research and Development, Jan., 1990, pp. 78-84.
[13] N.R. Saxena, "Test Compression Methods," MS thesis, Univ. of Iowa, May 1984.
[14] N.R. Saxena, E.J. McCluskey, and P. Franco, "Bounds on Signature Analysis Aliasing for Random Testing," Proc. FTCS, pp. 104-111, 1991.
[15] N.R. Saxena, P. Franco, and E.J. McCluskey, "Refined Bounds on Signature Analysis Aliasing for Random Testing," ITC '91 Proc., pp. 818-827, Oct. 1991.
[16] N.R. Saxena, P. Franco, and E.J. McCluskey, "Simple Bounds on Serial Signature Analysis Aliasing for Random Testing," Special Issue on Fault Tolerant Computing, IEEE Trans. Computers, vol. 41, no. 5, pp. 638-645, May 1992.
[17] M. Serra et al., "The Analysis of One-Dimensional Linear Cellular Automata and Their Aliasing Properties," IEEE Trans. Computer-Aided Design, vol. 9, no. 7, pp. 767-778, July 1990.
[18] J.J. Shedletsky, "Random Testing: Practicality vs. Verified Effectiveness," Proc. 17th Ann. Int'l Conf. Fault-Tolerant Computing, pp. 175-179, June 1977.
[19] T.W. Williams et al., "Aliasing Errors in Signature Analysis," IEEE Design and Test of Computers, pp. 39-45, Apr. 1987.
[20] T.W. Williams et al., "Aliasing Errors in Multiple Input Signature Analysis Registers," Proc. European Test Conf., pp. 338-345, Apr. 1989.
[21] M. Damiani et al., "Aliasing in Signature Analysis Testing with Multiple-Input Shift Registers," Proc. European Test Conf., pp. 346-353, Apr. 1989.
[22] N. Benowitz et al., "An Advanced Fault Isolation System for Digital Logic," IEEE Trans. Computers, vol. 24, no. 5, pp. 489-497, May 1975.
[23] R.A. Frohwerk, "Signature Analysis: A New Digital Field Service Method," Hewlett-Packard J., pp. 2-8, May 1977.
[24] D.K. Pradhan and S. Gupta, A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression IEEE Trans. Computers, vol. 40, no. 6, June 1991.
[25] I. Pomeranz, S.M. Reddy, and R. Tangirala, "On Achieving Zero Aliasing for Modeled Faults," Proc. EDAC, 1992.
[26] J.L. Carter, "The Theory of Signature Testing for VLSI," Proc. 14th ACM Symp. Theory of Computing, pp. 66-76,San Francisco, May 1982.
[27] A. Gill, Linear Sequential Circuits—Analysis, Synthesis, and Applications. McGraw-Hill, 1966.
[28] W.W. Peterson and E.J. Weldon Jr., Error-Correcting Codes, second edition. The MIT Press, 1984.
[29] R.L. Graham, D.E. Knuth, and O. Patashnik, Concrete Mathematics- A Foundation for Computer Science. Addison-Wesley, 1989.
[30] M.G. Karpovsky, S.K. Gupta, and D.K. Pradhan, "Aliasing and Diagnosis in MISR and STUMPS Using General Error Model," ITC '91 Proc., pp. 828-839, Oct. 1991.
[31] K. Iwasaki et al., "Analysis of Aliasing Probability for MISRs by Using Complete Weight Distributions," IEICE Trans. Fundamentals, vol. E78-A, no. 12, pp. 1,691-1,698, Dec. 1995.

Index Terms:
Signature analysis, aliasing probability bounds, random testing, linear feedback shift registers, parallel signature designs, multiple input signature registers (MISR).
Citation:
Nirmal R. Saxena, Edward J. McCluskey, "Parallel Signature Analysis Design with Bounds on Aliasing," IEEE Transactions on Computers, vol. 46, no. 4, pp. 425-438, April 1997, doi:10.1109/12.588057
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