Issue No.02 - February (1997 vol.46)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.565614
<p><b>Abstract</b>—This brief contribution presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 μm static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.</p>
Carry lookahead adders, carry-select adders, conditional-sum adders, conditional carry adders, Manchester carry chain, spanning tree carry lookahead.
Jien-Chung Lo, "A Fast Binary Adder with Conditional Carry Generation", IEEE Transactions on Computers, vol.46, no. 2, pp. 248-253, February 1997, doi:10.1109/12.565614