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A Fast Binary Adder with Conditional Carry Generation
February 1997 (vol. 46 no. 2)
pp. 248-253

Abstract—This brief contribution presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 μm static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.

[1] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[2] J. Sklansky, "Conditional-Sum Addition Logic," IRE Trans. Electronic Computers, vol. 9, no. 6, pp. 226-231, June 1960.
[3] I. Koren, Computer Arithmetic Algorithms.Englewood Cliffs, N.J.: Prentice Hall, 1993.
[4] B. Becker and R. Kolla, "On the Construction of Optimal Time Adders," Proc. STACS 88, G. Goos and J. Hartmanis, eds., Lecture Notes in Computer Science, pp. 18-28, Springer-Verlag, Feb. 1988.
[5] I.S. Hwang and A.L. Fisher, "A 3.1 ns 32 b CMOS Adder in Multiple Output Domino Logic," IEEE J. Solid-State Circuits, vol. 24, pp. 358-369, Apr. 1989.
[6] A. Naini, D. Bearden, and W. Anderson, "A 4.5 ns 96 b CMOS Adder Design," Proc. Custom Integrated Circuits Conf., May 1992.
[7] H.R. Srinivas and K.P. Keshab,“A fast VLSI adder architecture,” IEEE J. Solid-State Circuits, vol. 27, no. 5, pp. 761-767, May 1992.
[8] T. Lynch and E.E. Swartzlander, "A Spanning Tree Carry Lookahead Adder," IEEE Trans. Computers, vol. 41, no. 8, pp. 931-939, Aug. 1992.
[9] V. Kantabutra, "A Recursive Carry-Lookahead/Carry-Select Hybrid Adder," IEEE Trans. Computers, vol. 42, no. 12, pp. 1,495-1,499, Dec. 1993.
[10] H. Ling, "High-Speed Binary Adder," IBM J. Research and Development, vol. 25, pp. 156-166, May 1981.
[11] V. Kantabutra, "Designing One-Level Carry-Skip Adders," IEEE Trans. Computers, vol. 42, no. 6, pp. 759-764, June 1993.

Index Terms:
Carry lookahead adders, carry-select adders, conditional-sum adders, conditional carry adders, Manchester carry chain, spanning tree carry lookahead.
Citation:
Jien-Chung Lo, "A Fast Binary Adder with Conditional Carry Generation," IEEE Transactions on Computers, vol. 46, no. 2, pp. 248-253, Feb. 1997, doi:10.1109/12.565614
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