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| Jien-Chung Lo, "A Fast Binary Adder with Conditional Carry Generation," IEEE Transactions on Computers, vol. 46, no. 2, pp. 248-253, February, 1997. | |||
| BibTex | x | ||
| @article{ 10.1109/12.565614, author = {Jien-Chung Lo}, title = {A Fast Binary Adder with Conditional Carry Generation}, journal ={IEEE Transactions on Computers}, volume = {46}, number = {2}, issn = {0018-9340}, year = {1997}, pages = {248-253}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.565614}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Fast Binary Adder with Conditional Carry Generation IS - 2 SN - 0018-9340 SP248 EP253 EPD - 248-253 A1 - Jien-Chung Lo, PY - 1997 KW - Carry lookahead adders KW - carry-select adders KW - conditional-sum adders KW - conditional carry adders KW - Manchester carry chain KW - spanning tree carry lookahead. VL - 46 JA - IEEE Transactions on Computers ER - | |||
Abstract—This brief contribution presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 μm static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit.
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