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Topologies of Combined (2logN - 1)-Stage Interconnection Networks
January 1997 (vol. 46 no. 1)
pp. 118-124

Abstract—A combined (2logN − 1)-stage interconnection network (denoted by $\Delta \oplus \Delta '$) is constructed by concatenating two Omega-equivalent networks (Δ and Δ′) with the rightmost stage of Δ and the leftmost stage of Δ′ overlapped. Benes network and the (2logN − 1)-stage shuffle-exchange network are two examples of such networks. Although these two networks have received intensive studies, the research on the topology of entire class of $\Delta \oplus \Delta '$ networks is very limited so far. In this paper, we study the topological structure of $\Delta \oplus \Delta '$ networks and propose an algorithm for determining topological equivalence between two given $\Delta \oplus \Delta '$ networks. We also present a simplified Ω-equivalence checking algorithm as a supporting result.

[1] D.P. Agrawal, "Graph Theoretical Analysis and Design of Multistage Interconnection Networks," IEEE Trans. Computers, vol. 32, no. 7, pp. 637-648, July 1983.
[2] K.E. Batcher, "The Flip Network in STARAN," Proc. 1976 Int'l Conf. Parallel Processing, pp. 65-71, 1976.
[3] V.E. Benes, "On Rearrangeable Three-Stage Connecting Networks," The Bell System Technical J., vol. XLI, no. 5, pp. 1,481-1,492, Sept. 1962.
[4] D.M. Dias and J.R. Jump, "Analysis and Simulation of Buffered Delta Networks," IEEE Trans. Computers, vol. 30, no. 4, pp. 273-282, Apr. 1981.
[5] T. Feng, "A Survey of Interconnection Networks," Computer, pp. 12-27, Dec. 1981.
[6] T. Feng, "Data Manipulating Functions in Parallel Processors and Implementations," IEEE Trans. Computers, vol. 23, no. 5, pp. 309-318, May. 1974.
[7] T. Feng, Y. Kim, and S. Seo, "Interstage Correlations in a Class of Multistage Interconnection Networks," Proc. 1994 Int'l Computer Symp., 1994.
[8] L. R. Goke and G. J. Lipovski,“Banyan networks for partitioning multiprocessor systems,”inFirst Ann. Symp. Comput. Archit., 1973, pp. 21–28.
[9] G. Bilardi, "Merging and Sorting Networks with the Topology of the Omega Network," IEEE Trans. Computers, vol. 38, no. 10, Oct. 1989.
[10] D.H. Lawrie, "Access and Alignment of Data in an Array Processor," IEEE Trans. Computers, vol. 24, no. 12, pp. 1,145-1,155, Dec. 1975.
[11] K.Y. Lee, "On the Rearrangeability of (2logN−1) Stage Permutation Networks," IEEE Trans. Computers, vol. 34, no. 5, pp. 412-425, May 1985.
[12] F.T. Leighton,Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes.San Mateo, Calif.: Morgan Kaufmann, 1992.
[13] M.C. Pease, "The Indirect Binary n-cube Microprocessor Array," IEEE Trans. Computers, vol. 26, no. 5, pp. 458-473, May 1977.
[14] H.J. Siegel and S.D. Smith, "Study of Multistage SIMD Interconnection Networks," Proc. Fifth Symp. Computer Architecture, pp. 223-229, Apr. 1978.
[15] C. Wu and T. Feng, "On a Class of Multistage Interconnection Networks," IEEE Trans. Computers, vol. 29, no. 8, pp. 694-702, Aug. 1980.
[16] C. Wu and T. Feng, "The Reverse-Exchange Interconnection Network," IEEE Trans. Computers, vol. 29, no. 9, pp. 801-811, Sept. 1980.
[17] Y.-M. Yeh, T.-Y. Feng, "On a Class of Rearrangeable Networks," IEEE Trans. Computers, vol. 41, no. 11, pp. 1,361-1,379, Nov. 1992.

Index Terms:
Combined (2logN − 1)-stage network, equivalence, multistage interconnection network, permutation, topology, Ω-equivalent class
Qing Hu, Xiaojun Shen, Jingyu Yang, "Topologies of Combined (2logN - 1)-Stage Interconnection Networks," IEEE Transactions on Computers, vol. 46, no. 1, pp. 118-124, Jan. 1997, doi:10.1109/12.559812
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