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A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-
January 1997 (vol. 46 no. 1)
pp. 105-109

Abstract—A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a b-bit-per-chip manner, b≥ 2, and more efficient than previously known codes with as strong error control capabilities.

[1] T.R.N. Rao and Fujiwara, Error-Coding for Computer Systems.Englewood Cliffs, N.J.: Prentice Hall, 1989.
[2] F.J. McWilliams and N.J.A. Sloane, The Theory of Error-Correcting Codes. North-Holland, 1977.
[3] S.J. Hong and A.M. Patel, "A General Class of Maximal Codes for Computer Applications," IEEE Trans. Computers, vol. 21, no. 12, pp. 1,322-1,331, Dec. 1972.
[4] C. Chen,“Error-correcting codes for byte-organized memory systems,” IEEE Trans. Information Theory, vol. 32, pp. 181-185, Mar. 1986.
[5] C.L. Chen, "Symbol Error-Correcting Codes for Computer Memory Systems," IEEE Trans. Computers, vol. 41, no. 2, pp. 252-256, Feb. 1992.
[6] I.S. Reed and G. Solomon, "Polynomial Codes Over Certain Finite Fields," J. S IA M., vol. 8, pp. 300-304, 1960.
[7] J.K. Wolf, "Adding Two Information Symbols to Certain Nonbinary BCH Codes and Some Applications," Bell Systems Technical J., vol. 48, pp. 2,405-2,424, Sept., 1969.
[8] R.C. Singleton, "Maximum Distance Q-Nary Codes," IEEE Trans. Information Theory, vol. 10, pp. 116-118, Apr. 1964.
[9] D.C. Bossen, L.C. Chang, and C.L. Chen, "Measurement and Generation of Error Correcting Codes for Package Failures," IEEE Trans. Computers, vol. 27, no. 3, pp. 201-204, Mar. 1978.
[10] S.M. Reddy, "A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems," IEEE Trans. Computers, vol. 27, no. 5, pp. 455-459, May 1978.

Index Terms:
Error correcting code, byte, soft error, subfield, minimum polynomial.
Citation:
Mitsuru Hamada, Eiji Fujiwara, "A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-," IEEE Transactions on Computers, vol. 46, no. 1, pp. 105-109, Jan. 1997, doi:10.1109/12.559809
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