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Issue No.01 - January (1997 vol.46)
pp: 105-109
ABSTRACT
<p><b>Abstract</b>—A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a <it>b</it>-bit-per-chip manner, <it>b</it>≥ 2, and more efficient than previously known codes with as strong error control capabilities.</p>
INDEX TERMS
Error correcting code, byte, soft error, subfield, minimum polynomial.
CITATION
Mitsuru Hamada, Eiji Fujiwara, "A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-", IEEE Transactions on Computers, vol.46, no. 1, pp. 105-109, January 1997, doi:10.1109/12.559809
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