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On Dictionary-Based Fault Location in Digital Logic Circuits
January 1997 (vol. 46 no. 1)
pp. 48-59

Abstract—In this work, fault location based on a fault dictionary is considered at the chip level. To justify the use of a precomputed dictionary in terms of computation time, the computational effort invested in computing a dictionary is first analyzed. The number of circuit diagnoses that need to be performed dynamically, without the use of precomputed knowledge, before the overall diagnosis effort exceeds the effort of computing a dictionary, is studied. Experimental results on ISCAS-85 circuits show that for relatively small numbers of diagnoses, a precomputed dictionary is more efficient than dynamic diagnosis. Next, a method to derive small dictionaries without losing resolution of modeled faults is proposed, based on extended pass/fail analysis. The same procedure is applicable for selecting internal observation points to increase the resolution of the test set. Methods to compact the resulting dictionary further, using compaction techniques generally applied to fault detection, are then described. Experimental results are presented to demonstrate the effectiveness of the proposed methods.

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Index Terms:
Compact fault dictionary, dynamic fault diagnosis, fault diagnosis, fault dictionary.
Citation:
Irith Pomeranz, Sudhakar M. Reddy, "On Dictionary-Based Fault Location in Digital Logic Circuits," IEEE Transactions on Computers, vol. 46, no. 1, pp. 48-59, Jan. 1997, doi:10.1109/12.559802
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