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Optimal Data Scheduling for Uniform Multidimensional Applications
December 1996 (vol. 45 no. 12)
pp. 1439-1444

Abstract—Uniform nested loops are broadly used in scientific and multidimensional digital signal processing applications. Due to the amount of data handled by such applications, on-chip memory is required to improve the data access and overall system performance. In this study a static data scheduling method, carrot-hole data scheduling, is proposed for multidimensional applications, in order to control the data traffic between different levels of memory. Based on this data schedule, optimal partitioning and scheduling are selected. Experiments show that by using this technique, on-chip memory misses are significantly reduced as compared to results obtained from traditional methods. The carrot-hole data scheduling method is proven to obtain smallest on-chip memory misses compared with other linear scheduling and partitioning schemes.

[1] S. Abraham and D. Hudak, "Compile-Time Partitioning of Iterative Parallel Loops to Reduce Cache Coherence Traffic," IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 3, July 1991.
[2] A. Agarwal, D. Kranz, and V. Natarajan, "Automatic Partitioning of Parallel Loops for Cache-Coherent Multiprocessors," Proc. 1993 Int'l Conf. Parallel Processing, pp. 2-11, 1993.
[3] W.P. Burleson, "The Partitioning Problem on VLSI Arrays: I/O And Local Memory Complexity," Proc. 1991 Int'l Conf. Acoustics, Speech, and Signal Processing, pp. 1,217-1,220, 1991.
[4] L.-F. Chao and E.H.-M. Sha, "Static Scheduling of Uniform Nested Loops," Proc. Seventh Int'l Parallel Processing Symp., pp. 1,421-1,424,Newport Beach, Calif., Apr. 1993.
[5] T-S. Chen and J-P. Sheu, "Communication-Free Data Allocation Techniques for Parallelizing Compilers on Multicomputers," IEEE Trans. Parallel and Distributed Systems, vol. 5, no. 9, Sept. 1994, pp. 924-938.
[6] A. Darte and Y. Robert, "Constructive Methods for Scheduling Uniform Loop Nests," IEEE Trans. Parallel and Distributed Systems, vol. 5, Aug. 1994.
[7] H.W. Emmons, "Critique of Numerical Modeling of Fluid Mechanics," Ann. Rev. Fluid Mechanics, vol. 2, pp. 15-36, 1970.
[8] D. Gajski et al., High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992.
[9] K. Jainandunsing, "Optimal Partitioning Schemes for Wavefront/Systolic Array Processors," Proc. IEEE Symp. Circuits and Systems, pp. 940-943, 1986.
[10] S.Y. Kung, VLSI Array Processors. Prentice Hall, 1988.
[11] D.I. Moldovan and J.A.B. Fortes, “Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays,” IEEE Trans. Computers, vol. 35, no. 1, pp.1-12, Jan. 1986.
[12] N.L. Passos, E.H.-M. Sha, and S.C. Bass, "Partitioning and Retiming of Multidimensional Systems," to appear in Proc. IEEE Int'l Conf. Circuits and Systems,London, May 1994.
[13] N. Passos and E. H.-M. Sha, "Full Parallelism of Uniform Nested Loops by Multi-Dimensional Retiming," Proc. Int'l Conf. Parallel Processing, vol. 2, pp. 130-133, 1994.
[14] I.M. Verbauwhede, C.J. Scheers, and J.M. Rabaey, "Memory Estimation for High Level Synthesis," Proc. 31st ACM/IEEE Design Automation Conf., pp. 143-148, 1994.
[15] I.M. Verbauwhede, F. Catthoor, J. Vandewalle, and H. De Man, "In-Place Memory Management of Algebraic Algorithms on Application-Specific ICs," J. VLSI Signal Processing, vol. 3, pp. 193-200, 1991.
[16] I.M. Verbauwhede, F. Catthoor, J. Vandewalle, and H. De Man, "Background Memory Synthesis for Algebraic Algorithms on Multi-Processor DSP Chips" VLSI'89, Proc. Int'l Conf. Very Large Scale Integration, pp. 209-218, Aug. 1989.

Index Terms:
Execution scheduling, data scheduling, nested loops, memory management, memory hierarchy, partitioning, digital signal processing, multidimensional application.
Citation:
Qingyan Wang, Nelson Luiz Passos, Edwin Hsing-Mean Sha, "Optimal Data Scheduling for Uniform Multidimensional Applications," IEEE Transactions on Computers, vol. 45, no. 12, pp. 1439-1444, Dec. 1996, doi:10.1109/12.545974
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