This Article 
 Bibliographic References 
 Add to: 
On the Use of Counters for Reproducing Deterministic Test Sets
December 1996 (vol. 45 no. 12)
pp. 1405-1419

Abstract—We propose a very simple and fast CAD tool to check whether a binary counter can reproduce a predetermined set of test patterns in a reasonable time. Given a test matrix T, the tool uses column merging, complementation, and permutation so that the distance between the starting and the finishing vector of the corresponding counter is minimized. The hardware overhead of the proposed approach is by far lower than that of any other existing approach. Although it is computationally difficult (NP-hard) to obtain the absolute minimum distance, we present an algorithm which in the absence of don't cares in the test matrix, finds an appropriate column merging, complementation, and permutation that guarantees the distance is never more than twice as large as the best possible. In the presence of don't cares, the latter algorithm forms the basis of a powerful heuristic. Experiments on various test sets on benchmark circuits show that the exact number of clock cycles needed for a binary counter to reproduce all the patterns for the hard-to-detect faults compares favorably with the expected number yielded by existing Weighted Random LFSR-based approaches which have significantly higher hardware overhead.

[1] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design.New York: Computer Science Press, 1990.
[2] V.K. Agarwal and E. Cerny, "Store and Generate Built-In Testing Approach," Proc. Int'l Symp. Fault-Tolerant Computing, pp. 35-40, 1981.
[3] P. Agrawal and V.D. Agrawal, "On Monte Carlo Testing of Logic Networks," IEEE Trans. Computers, vol. 15, no. 6. pp. 664-667, 1976.
[4] S. Akers and W. Jansz, Test Set Embedding in a BIST Environment Proc. Int'l Test Conf., pp. 257-263, 1989.
[5] P.H. Bardell, W.H. McAnney, and J. Savir, Built-In Test for VLSI, John Wiley&Sons, New York, 1987.
[6] S. Bouzebari and B. Kaminska, "A Deterministic Built-In Self-Test Generator Based on Cellular Automata Structures," IEEE Trans. Computers, vol. 44, no. 6, pp. 805-814, June 1995.
[7] F. Brglez, C. Gloster, and G. Kedem, "Built-In Self-Test with Weighted Random Pattern Hardware," Proc. ICCD, pp. 161-166, 1990.
[8] W. Daehn and J. Mucha, "Hardware Test Pattern Generators for Built-in Test," Proc. Int'l Test Conf., pp. 110-113, 1981.
[9] R. Dandapani, J. Patel, and J. Abraham, "Design of Test Pattern Generators for Built-In Test," Proc. Int'l Test Conf., pp. 315-319, 1984.
[10] A.K. Das, M. Pandey, and A. Gupta, "Built-In Self-Test Structures Around Cellular Automata and Counters," IEE Proc. Part E: Computers and Digital Techniques, vol. 137, no. 4, pp. 269-274, 1990.
[11] C. Dufaza and G. Gambon, "LFSR-Based Deterministic and Pseudo-Random Test Pattern Generator Structures," Proc. European Test Conf., pp. 27-34, 1991.
[12] C. Dufaza and L.F.C. Lew Yan Voon, "BIST Generator Based on Asynchronous Counter," Proc. Workshop New Directions for Testing, pp. 229-232, 1992.
[13] C. Dufaza et al., BIST Hardware Generator for Mixed Test Scheme Proc. European Design and Test Conf., 1995.
[14] H. Fujiwara and T. Shimono, "On the Acceleration of Test Generation Algorithms," IEEE Trans. Computers, vol. 32, no. 12, pp. 1,137-1,144, Dec. 1983.
[15] M.R. Garey and D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness.New York: W.H. Freeman, 1979.
[16] S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," Proc. IEEE Int'l Test Conf., pp. 120-129, 1992.
[17] P.D. Hortensius et al., “Cellular Automata Circuits for Built-In Self Test,” IBM J. Research and Development, vol. 34, March/May 1990.
[18] B. Koenemann, "LFSR-Coded Test Patterns for Scan Designs," Proc. European Test Conf., pp. 231-242, 1991.
[19] A. Kunzmann, "FPGA-Based Self-Test with Deterministic Test Patterns," Proc. Second Int'l Workshop Field-Programmable Logic and Applications, 1992 pp. 175-182, Springer-Verlag LNCS 705, 1993.
[20] A. Majumdar, “A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing,” Proc. Int'l Conf. Computer Design, pp. 288-291, 1994.
[21] F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, A New Procedure for Weighted Random Built-In-Self-Test Proc. Int'l Test Conf., pp. 660-668, 1990,
[22] D.J. Neebel and C.R. Kime, "Inhomogeneous Cellular Automata for Weighted Random Pattern Generation," Proc. Int'l Test Conf., pp. 1,013-1,022. IEEE, 1993.
[23] I. Pomeranz and S.M. Reddy, “3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits,” IEEE Trans. Computer-Aided Design, vol. 12, no. 7, pp. 1,050-1,058, July 1993.
[24] J. Van Sas, F. Catthoor, and H. De Man, "Cellular Automata Based Deterministic Self-Test Strategies for Programmable Data Paths," IEEE Trans. Computer-Aided Design, vol. 13, no. 7, pp. 940-953, 1994.
[25] H. Wunderlich, Multiple Distributions of Biased Random Test Patterns IEEE Trans. Computer-Aided Design, vol. 9, no. 6, June 1990.

Index Terms:
Built-in self-test, test pattern generation, deterministic test set, binary counter, binary matrix column permutations.
Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar, "On the Use of Counters for Reproducing Deterministic Test Sets," IEEE Transactions on Computers, vol. 45, no. 12, pp. 1405-1419, Dec. 1996, doi:10.1109/12.545970
Usage of this product signifies your acceptance of the Terms of Use.