Issue No.12 - December (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.545969
<p><b>Abstract</b>—We address test data compaction for built-in self-test (BIST). We propose a novel taxonomy useful for classifying and comparing BIST compactors. The taxonomy uses the following attributes: space, time, memory, linearity, and circuit (functional) specificity. The thrust of the work focuses on BIST <it>space</it> compaction, a process increasingly required when a large number of internal circuit nodes need to be monitored during test but where area limitations preclude the association of observation latches for all the monitored nodes. We introduce a general class of space compactors denoted as <it>programmable space compactors</it> (PSCs). Programmability enables highly-effective space compactors to be designed for circuits under test (CUT) subjected to a specific set of test patterns. Circuit-specific information such as the fault-free and expected faulty behavior of a circuit are used to choose PSCs that have better fault coverage and/or lower area costs than the commonly-used parity function. Finding optimal PSCs is a difficult task since the space of possible PSC functions is extremely large and grows exponentially with the number of lines (nodes) to be compacted. We describe an optimization search method based on genetic algorithms for finding combinational PSCs. The factors used to assess the effectiveness of a PSC are its fault coverage and implementation area. Results reveal that we can find PSCs with better fault coverage and cost characteristics than the parity function using modest computing resources, e.g., PSCs with equal or greater fault coverage than the parity function for as little as 20% of the cost (in terms of gate count) with an investment of only a few hours of workstation computing time.</p>
Testing, Built-In Self-Test (BIST), design for testability, BIST methodologies, BIST space compaction, genetic algorithms, parity tree, BIST compaction.
André Ivanov, Barry K. Tsuji, Yervant Zorian, "Programmable BIST Space Compactors", IEEE Transactions on Computers, vol.45, no. 12, pp. 1393-1404, December 1996, doi:10.1109/12.545969