This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR)
December 1996 (vol. 45 no. 12)
pp. 1370-1378

Abstract—We propose a backward angle recoding (BAR) method to eliminate redundant CORDIC elementary rotations and hence expedite the CORDIC rotation computation. We prove that for each of the linear, circular, and hyperbolic CORDIC rotations, the use of BAR guarantees more than 50% reduction of elementary CORDIC rotations provided the scaling factor needs not be kept constant. The proposed BAR algorithm is simple, and amenable to VLSI implementation. Taking practical applications into consideration, we discuss how to incorporate convergence range enhancement procedure with BAR, and how easy it is to devise a constant-scaling-factor BAR algorithm while still enjoying 25% reduction of CORDIC elementary rotations.

[1] H.M. Ahmed,“Signal processing algorithms and architectures,” PhD dissertation, Dept. of Electrical Eng., Stanford Univ., June 1982.
[2] H.M. Ahmed and K.H. Fu, "A VLSI Array CORDIC Architecture," Proc. ICASSP '89, pp. 2,385-2,388,Glasgow, Scotland, 1989.
[3] J.D. Bruguera, E. Antelo, and E.L. Zapata, "Design of a Pipelined Radix-4 CORDIC Processor," J. Parallel Computing, vol. 19, no. 7, pp. 729-744, 1993.
[4] J.R. Cacallaro and F.T. Luk,"CORDIC Arithmetic for a SVD Processor," J. Parallel and Distributed Computing, vol. 5, pp. 271-290, 1988.
[5] T.W. Curtis, P. Allison, and J.A. Howard, "A CORDIC Processor for Laser Trimming," IEEE Micro, vol. 6, no. 3, pp. 61-71, 1986.
[6] A.A.J. De Lange, A.J. Vander Hoeven, E.F. Deprettere, and J. Bu, "An Optimal Floating Point Pipeline CMOS CORDIC Processor," Proc. ISCAS,Espoo, Finland, 1988.
[7] A.A.J. De Lange, E.F. Deprettere, A.J. Vander Veen, and J. Bu, "Real Time Applications of the Floating Point Pipeline CORDIC Processor in Massive-Parallel Pipelined DSP Algorithms," Proc. ICASSP, pp. 1,013-1,016, 1990.
[8] J.M. Delosme, "The Matrix Exponential Approach to Elementary Operations," Proc. SPIE, vol. 696, pp. 188-195, 1987.
[9] E.F. Deprettere, "Synthesis and Fixed Point Implementation of Pipelined True Orthogonal Filters," Proc. ICASSP, pp. 217-220,Boston, 1983.
[10] P. Dewilde, E.F. Deprettere, and R. Nouta, "Parallel and Pipelined VLSI Implementation of Signal Processing Algorithms," VLSI and Modern Signal Processing, S.Y. Kung et al., eds. Prentice Hall, 1985.
[11] R.G. Harber, X. Hu, J. Li, and S.C. Bass, "The Application of Bit-Serial CORDIC Computational Units to the Design of Inverse Kinematics Processors," Proc. IEEE Int'l Conf. Robotics and Automation,Philadelphia, 1988.
[12] G.L. Haviland and A.A. Tuszynski, "A CORDIC Arithmetic Processor Chip," IEEE Trans. Computers, vol. 29, no. 2, pp. 68-79, Feb. 1980.
[13] J.P. Hayes,Computer Architecture and Organization, Second Edition, McGraw-Hill, 1988.
[14] X. Hu and R.G. Harber,“Expanding the range of convergence of the CORDIC algorithm,” IEEE Trans. Computers, vol. 40, no. 1, pp. 13-21, Jan. 1991.
[15] Y.H. Hu, "Pipelined CORDIC Architecture for the Implementation of Rotation-Based Algorithms," Proc. Int'l Symp. VLSI Technology, Systems, and Algorithms,Taipei, Taiwan, Republic of China, 1985.
[16] Y.H. Hu and S.Y. Kung, "Toeplitz Eigen-System Solver," IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 33, no. 5, pp. 1,264-1,271, 1985.
[17] Y.H. Hu,"The Quantization Effects of the CORDIC Algorithm," IEEE Trans. Circuits and Systems, vol. 40, no. 4, pp. 834-844, 1992.
[18] Y.H. Hu and P.H. Milenkovic, "A Fast Least Square Deconvolution Algorithm for Vocal Tract Cross-Section Estimation," IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 38, no. 6, pp. 921-924, 1990.
[19] Y.H. Hu and S. Naganathan, "A Novel Implementation of Chirp-Z Transform Using a CORDIC Processor," IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 38, no. 2, pp. 3532-354, 1990.
[20] Y.H. Hu and H.M. Chern, "VLSI CORDIC Array Structure Implementation of Toeplitz Eigensystem Solvers," Proc. ICASSP, pp. 1,575-1,578, 1990.
[21] Y.M. Hu, “CORDIC-Based VLSI Architectures for Digital Signal Processing,” IEEE Signal Processing Magazine, vol. 9, pp. 16-35, 1992.
[22] Y.H. Hu and S. Naganathan, "An Angle Recoding Method for CORDIC Algorithm Implementation," IEEE Trans. Computers, vol. 42, no. 1, pp. 99-102, Jan. 1993.
[23] Y.H. Hu, "A Forward Angle Recoding CORDIC Algorithm and Pipelined Processor Array Structure for Digital Signal Processing," Digital Signal Processing P A Review J., vol. 3, no. 1, pp. 2-15, 1993.
[24] Y.H. Hu and Z. Wu, "An Efficient CORDIC Array Structure for the Implementation of Discrete Cosine Transform," IEEE Trans. Signal Processing, vol. 43, no. 1, pp. 331-336, 1995.
[25] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[26] K. Jainandunsing and E.F. Deprettere, "A New Class of Parallel Algorithm for Solving Systems of Linear Equation," SIAM J. Science and Statistical Computing, vol. 10, no. 5, pp. 880-912, 1989.
[27] D.T.L. Lee and M. Morf, "Generalized CORDIC for Digital Signal Processing," Proc. Int'l Conf. Acoustics, Speech, and Signal Processing,Paris, 1982.
[28] J. Lee and T. Lang,"Constant-Factor Redundant CORDIC for Angle Calculation and Rotation," IEEE Trans. Computers, vol. 41, no. 8, pp. 1,016-1,035, Aug. 1992.
[29] C.M. Rader, D.L. Allen, D.B. Glasco, and C.E. Woodward, "MUSE P A Systolic Array for Adaptive Nulling with 64 Degrees of Freedom, Using Givens Transformations and Wafer Scale Integration," MIT Lincoln Laboratory, May18, 1990.
[30] T.Y. Sung, Y.H. Hu, and H.J. Yu, "Doubly Pipelined CORDIC Array Processor for Solving Toeplitz Systems," Proc. 23rd Allerton Conf. Comm., Control, and Computing,Monticello, Ill., 1985.
[31] T.Y. Sung, T. Parng, Y. Hu, and H.J. Yu, "Design and Implementation of a VLSI CORDIC Processor," Proc. Int'l Symp. Circuits and Systems, pp. 934-935,San Jose, Calif., 1986.
[32] T.Y. Sung, Y.H. Hu, and H.J. Yu, "Doubly Pipelined CORDIC Array for Digital Signal Processing Algorithms," Proc. Int'l Conf. Acoustics, Speech, and Signal Processing, pp. 69-72,Tokyo, 1986.
[33] D. Timmerman, H. Hahn, B.J. Hosicka, and G. Schmidt, "A Programmable CORDIC Chip for Digital Signal Processing Applications," IEEE J. Solid-State Circuits, vol. 26, no. 9, pp. 1,317-1,321, 1991.
[34] R. Udo, E. Deprettere, and P. Dewilde, "On the Implementation of Orthogonal and Orthogonalizing Algorithms Using Pipelined CORDIC Architectures," Proc. Second European Signal Processing Conf.,Erlangen, Germany, 1983.
[35] J.E. Volder, "The CORDIC Trigonometric Computing Technique," IRE Trans. Electronic Computers, vol. 8, no. 3, pp. 330-334, 1959.
[36] J.S. Walther, "A Unified Algorithms for Elementary Functions," Proc. Spring Joint Computer Conf., pp. 379-385, 1971.
[37] A.K. Yuen, "Intel's Floating-Point Processors," Proc. Electron '88,Boston, 1988.

Index Terms:
CORDIC, angle recoding, rotation based computing, VLSI, arithmetic unit, backward angle recoding.
Citation:
Yu Hen Hu, Homer H.M. Chern, "A Novel Implementation of CORDIC Algorithm Using Backward Angle Recoding (BAR)," IEEE Transactions on Computers, vol. 45, no. 12, pp. 1370-1378, Dec. 1996, doi:10.1109/12.545967
Usage of this product signifies your acceptance of the Terms of Use.