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Eric M. Schwarz, Michael J. Flynn, "Hardware Starting Approximation Method and Its Application to the Square Root Operation," IEEE Transactions on Computers, vol. 45, no. 12, pp. 13561369, December, 1996.  
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@article{ 10.1109/12.545966, author = {Eric M. Schwarz and Michael J. Flynn}, title = {Hardware Starting Approximation Method and Its Application to the Square Root Operation}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {12}, issn = {00189340}, year = {1996}, pages = {13561369}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.545966}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Hardware Starting Approximation Method and Its Application to the Square Root Operation IS  12 SN  00189340 SP1356 EP1369 EPD  13561369 A1  Eric M. Schwarz, A1  Michael J. Flynn, PY  1996 KW  Computer arithmetic KW  approximation theory KW  square root KW  multiplication KW  counter tree KW  division. VL  45 JA  IEEE Transactions on Computers ER   
Abstract—Quadratically converging algorithms for highorder arithmetic operations typically are accelerated by a starting approximation. The higher the precision of the starting approximation, the less number of iterations required for convergence. Traditional methods have used lookup tables or polynomial approximations, or a combination of the two called piecewise linear approximations. This paper provides a revision and major extension to our study [1] proposing a nontraditional method for reusing the hardware of a multiplier. An approximation is described in the form of partial product array (PPA) composed of Boolean elements. The Boolean elements are chosen such that their sum is a highprecision approximation to a highorder arithmetic operation such as square root, reciprocal, division, logarithm, exponential, and trigonometric functions. This paper derives a PPA that produces in the worst case a 16bit approximation to the square root operation. The implementation of the PPA utilizes an existing 53 bit multiplier design requiring approximately 1,000 dedicated logic gates of function, additional repowering circuits, and has a latency of one multiplication.
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