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A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits
November 1996 (vol. 45 no. 11)
pp. 1312-1318

Abstract—Conditions are derived for robust testing of a path delay fault via a sequence of vectors applied at-speed. A simulator has been developed that uses the above conditions, along with the knowledge of paths that are robustly tested by the previous vectors, to determine the fault coverage obtained by such testing. The results demonstrate the existing fault simulators can overestimate robust path delay fault coverage by 5-15%.

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Index Terms:
Delay testing, robust path delay testing, at-speed delay testing, fault simulation.
Citation:
Yuan-Chieh Hsu, Sandeep K. Gupta, "A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits," IEEE Transactions on Computers, vol. 45, no. 11, pp. 1312-1318, Nov. 1996, doi:10.1109/12.544489
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