Issue No.11 - November (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.544488
<p><b>Abstract</b>—A new synchronizer design is presented. Current synchronizer designs have certain disadvantages, both in characterization and in the tradeoff between settling time and sampling rate, which are overcome in the new design. Two possible implementations of the synchronizer are discussed.</p>
Metastability, synchronizer, asynchronous, synchronization, synchronizer design, flip-flop, synchronous digital systems.
Jacqueline Walker, "A New Synchronizer Design", IEEE Transactions on Computers, vol.45, no. 11, pp. 1308-1311, November 1996, doi:10.1109/12.544488