This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Request Resubmission in a Blocking, Circuit-Switched, Interconnection Network
November 1996 (vol. 45 no. 11)
pp. 1282-1293

Abstract—In this paper, we study the delay performance of a circuit switched, self-routing Delta network. A gated hold protocol that retains partial path information is used to guarantee service of all requests. A novel technique that involves the construction of an easier to analyze dominant system is presented. A recursive expression for the probability mass function of the cycle time in the dominant system is derived. Comparison of the dominant system analysis with simulation of the actual system shows that the dominant system accurately predicts performance for low network loads. As network loads increase, the dominant system becomes worse at predicting behavior of the actual system. These results also help develop insight into how to trade off higher delay variability for increased throughput.

[1] J.H. Patel, "Performance of Processor-Memory Interconnections for Multiprocessors," IEEE Trans. Computers, vol. 30, no. 10, pp. 771-780, Oct. 1981.
[2] T-y. Feng, "A Survey of Interconnection Networks," Computer, pp. 12-28, Dec. 1981.
[3] C.P. Kruskal and M. Snir, "The Performance of Multistage Interconnection Networks for Multiprocessors," IEEE Trans. Computers, vol. 32, no. 12, pp. 1,091-1,098, Dec. 1983.
[4] P.G. Harrison and N.M. Patel, "The Representation of Multistage Interconnection Networks in Queueing Models of Parallel Systems," J. ACM, vol. 37, no. 4, pp. 863-898, Oct. 1990.
[5] P. Heidelberger and P.A. Franaszek, "Traffic Studies of Unbuffered Delta Networks," IBM J. Research and Development, vol. 35, nos. 1/2, pp. 288-299, Jan./Mar. 1991.
[6] C. Wu and M. Lee,"Performance Analysis of Multistage Interconnection Network Configurations and Operations," IEEE Trans. Computers, vol. 41, no. 1, pp. 18-27, Jan. 1992.
[7] S.-H. Hsiao and C.Y.R. Chen, "Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy," IEEE Trans. Parallel and Distributed Systems, vol. 3, no. 5, pp. 632-640, Sept. 1992.
[8] C.P. Kruskal and M. Snir, "Cost Performance Tradeoffs for Interconnection Networks," Discrete Applied Mathematics, 37/38, pp. 359-385, 1992.
[9] A. Bhattacharya, R.R. Rao, and T.-T. Lin, "Delay Analysis of Synchronous Circuit Switched Delta Networks," Proc. 1992 Int'l Parallel Processing Symp.,Newport Beach, Calif., 1992.
[10] P. Dietrich and R.R. Rao, "Delay Analysis of a Circuit Switched Interconnection Network Implementing a Gated Hold Strategy," Proc. Allerton Conf. Comm., Computing, and Control, Sept. 1993.

Index Terms:
Parallel processing, resubmission, nonblocking, protocols, interconnection network, performance.
Citation:
Paul Dietrich, Ramesh R. Rao, "Request Resubmission in a Blocking, Circuit-Switched, Interconnection Network," IEEE Transactions on Computers, vol. 45, no. 11, pp. 1282-1293, Nov. 1996, doi:10.1109/12.544484
Usage of this product signifies your acceptance of the Terms of Use.