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Issue No.11 - November (1996 vol.45)
pp: 1248-1256
ABSTRACT
<p><b>Abstract</b>—Mixed analog and digital mode simulators have been available for accurate α-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for α-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.</p>
INDEX TERMS
Single event upset, transient fault injection, transient fault modeling, transient fault simulation, fault-tolerance.
CITATION
Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi, "A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults", IEEE Transactions on Computers, vol.45, no. 11, pp. 1248-1256, November 1996, doi:10.1109/12.544481
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