This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults
November 1996 (vol. 45 no. 11)
pp. 1248-1256

Abstract—Mixed analog and digital mode simulators have been available for accurate α-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for α-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

[1] R.K. Iyer and D.J. Rossetti, "A Measurement-Based Model for Workload Dependence of CPU Errors," IEEE Trans. Computers, vol. 35, no. 6, pp. 511-519, June 1986.
[2] T.C. May and M.H. Woods, "Alpha-Particle-Induced Soft Errors in Dynamic Memories," IEEE Trans. Electronic Devices, vol. 26, no. 1, pp. 2-9, Jan. 1979.
[3] L.W. Nagel, "SPICE2: A Computer Program to Simulate Semiconductor Circuits," Electronic Research Laboratory, Univ. of California, Berkeley, Report ERL-M520, May 1975.
[4] R. Saleh, "Nonlinear Relaxation Algorithms for Circuit Simulation," Memorandum no. UCB/ERL M87/21, Electronic Research Laboratory, Univ. of California, Berkeley, 1987.
[5] E.L. Acuna, J.P. Dervenis, A.J. Pagones, F.L. Yang, and R.A. Saleh, “Simulation Techniques for Mixed Analog/Digital Circuits,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 353-363, Apr. 1990.
[6] G. Choi, R.K. Iyer, R. Saleh, and V. Carreno, "A Fault Behavior Model for an Avionic Microprocessor: A Case Study," Proc. Int'l Working Conf. Dependable Computing for Critical Applications, pp. 71-77, Aug. 1989.
[7] F.L. Yang and R.A. Saleh, "Simulation and Analysis of Transient Faults in Digital Circuits," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 258-264, Mar. 1992.
[8] K.W. Li, J.R. Armstrong, and J.G. Tront, "An HDL Simulation of the Effects of Single Event Upsets on Microprocessor Program Flow," IEEE Trans. Nuclear Science, vol. 31, no. 6, pp. 1,139-1,144, Dec. 1984.
[9] M. Rimén and J. Ohlsson, "A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection," Proc. Int'l Test Conf., pp. 696-704, Nov. 1992.
[10] E. Czeck and D. Siewiorek, "Effects of Transient Gate-Level Faults on Program Behavior," Proc. Int'l Symp. Fault-Tolerant Computing, pp. 236-243, 1990.
[11] H. Cha, E.M. Rudnick, G.S. Choi, J.H. Patel, and R.K. Iyer, "A Fast and Accurate Gate-Level Transient Fault Simulation Environment," Digest, 23rd Int'l Symp. Fault-Tolerant Computing, pp. 310-319, June 1993.
[12] G. Ries, G. Choi, and R. Iyer, "Device-Level Transient Fault Modeling," Proc. 24th Int'l Symp. Fault-Tolerant Computing, FTCS-24,Austin, Texas, pp. 76-83, 1994.
[13] H. Cha, "A Gate Level Simulator for Alpha-Particle-Induced Transient Faults," PhD dissertation, Univ. of Illi nois, Urbana-Champaign, Oct. 1994.
[14] F. Brglez, D. Bryan, and K. Kozminski, "Combinatorial Profiles of Sequential Benchmark Circuits," Proc. IEEE Int'l. Symp. Circuits and Systems, IEEE Computer Soc. Press, Los Alamitos, Calif., 1989, pp. 1929-1934.
[15] T.L. Quarles, "SPICE3 Version 3C1 Users Guide," Memorandum no. UCB/ERL M89/46, Electronic Research Laboratory, Univ. of California, Berkeley, Apr. 1989.
[16] G.C. Messenger, "Collection of Charge on Junction Nodes from Ion Tracks," IEEE Trans. Nuclear Science, vol. 29, no. 6, pp. 2,024-2,031, Dec. 1982.
[17] V.A. Carreno, G. Choi, and R.K. Iyer, "Analog-Digital Simulation of Transient-Induced Logic Errors and Upset Susceptibility of an Advanced Control System," NASA Technical Memorandum 4241, Nov. 1990.
[18] H. Cha and J.H. Patel, "A Logic-Level Model forα-Particle Hits in CMOS Circuits," Proc. Int'l Conf. Computer Design, pp. 538-542, Oct. 1993.
[19] OCTTOOLS-5.1 Part 1: User Guide, A. Casotto, ed., Electronic Research Laboratory, Univ. of California, Berkeley, Oct. 1991.
[20] M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design.New York: Computer Science Press, 1990.
[21] T.M. Niermann, W. Cheng, and J.H. Patel, "PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator," IEEE Trans. Computer-Aided Design, vol. 11, no. 2, pp. 198-207, Feb. 1992.
[22] W.-T. Cheng and S. Davidson, “Sequential Circuit Test Generator (STG) Benchmark Results,” Proc. Int’l Symp. Circuits and Systems, IEEE, Piscataway, N.J., 1989, pp. 1939-1941.

Index Terms:
Single event upset, transient fault injection, transient fault modeling, transient fault simulation, fault-tolerance.
Citation:
Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi, "A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults," IEEE Transactions on Computers, vol. 45, no. 11, pp. 1248-1256, Nov. 1996, doi:10.1109/12.544481
Usage of this product signifies your acceptance of the Terms of Use.