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| Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi, "A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults," IEEE Transactions on Computers, vol. 45, no. 11, pp. 1248-1256, November, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/12.544481, author = {Hungse Cha and Elizabeth M. Rudnick and Janak H. Patel and Ravishankar K. Iyer and Gwan S. Choi}, title = {A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {11}, issn = {0018-9340}, year = {1996}, pages = {1248-1256}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.544481}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults IS - 11 SN - 0018-9340 SP1248 EP1256 EPD - 1248-1256 A1 - Hungse Cha, A1 - Elizabeth M. Rudnick, A1 - Janak H. Patel, A1 - Ravishankar K. Iyer, A1 - Gwan S. Choi, PY - 1996 KW - Single event upset KW - transient fault injection KW - transient fault modeling KW - transient fault simulation KW - fault-tolerance. VL - 45 JA - IEEE Transactions on Computers ER - | |||
Abstract—Mixed analog and digital mode simulators have been available for accurate α-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for α-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.
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