Issue No.10 - October (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.543711
<p><b>Abstract</b>—Memory hierarchies have long been studied by many means: system building, trace-driven simulation, and mathematical analysis. Yet little help is available for the system designer wishing to quickly size the different levels in a memory hierarchy to a first-order approximation. In this paper, we present a simple analysis for providing this practical help and some unexpected results and intuition that come out of the analysis. By applying a specific, parameterized model of workload locality, we are able to derive a closed-form solution for the optimal size of each hierarchy level. We verify the accuracy of this solution against exhaustive simulation with two case studies: a three-level I/O storage hierarchy and a three-level processor-cache hierarchy. In all but one case, the configuration recommended by the model performs within 5% of optimal. One result of our analysis is that the first place to spend money is the cheapest (rather than the fastest) cache level, particularly with small system budgets. Another is that money spent on an n-level hierarchy is spent in a fixed proportion until another level is added.</p>
Cache, memory, and storage hierarchies; trace-driven simulations; optimization of cache configurations.
Peter M. Chen, Seth R. Silverman, Bruce L. Jacob, "An Analytical Model for Designing Memory Hierarchies", IEEE Transactions on Computers, vol.45, no. 10, pp. 1180-1194, October 1996, doi:10.1109/12.543711