Issue No.10 - October (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.543707
<p><b>Abstract</b>—In the absence of information about the layout, test generation, and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for <it>simulating I</it><sub><it>DDQ</it></sub><it>Tests</it> for <it>all two-line bridging faults</it> in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that: The problem of computing <it>I</it><sub><it>DDQ</it></sub> tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable; and, even under some pessimistic assumptions, a complete <it>I</it><sub><it>DDQ</it></sub> test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults.</p>
Bridging faults, fault simulation, IDDQ testing, test generation.
Sreejit Chakravarty, "Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits", IEEE Transactions on Computers, vol.45, no. 10, pp. 1131-1140, October 1996, doi:10.1109/12.543707