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Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits
October 1996 (vol. 45 no. 10)
pp. 1131-1140

Abstract—In the absence of information about the layout, test generation, and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating IDDQTests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that: The problem of computing IDDQ tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable; and, even under some pessimistic assumptions, a complete IDDQ test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults.

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Index Terms:
Bridging faults, fault simulation, IDDQ testing, test generation.
Citation:
Sreejit Chakravarty, Paul J. Thadikaran, "Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits," IEEE Transactions on Computers, vol. 45, no. 10, pp. 1131-1140, Oct. 1996, doi:10.1109/12.543707
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