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Architecture Technique Trade-Offs Using Mean Memory Delay Time
October 1996 (vol. 45 no. 10)
pp. 1089-1100

Abstract—Many architecture features are available for improving the performance of a cache-based system. These hardware techniques include cache memories, processor stalling characteristics, memory cycle time, the external data bus width of a processor, and pipelined memory system, etc. Each of these techniques affects the cost, design, and performance of a system. We present a powerful approach to assess the performance trade-offs of these architecture techniques based on the equivalence of mean memory delay time. For the same performance point, we demonstrate how each of these features can be traded off and report the ranking of the achievable performance of using them.

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Index Terms:
Bus width, cache hit ratio, memory cycle time, performance trade-off, pipelined memory, read-bypassing write buffer.
Citation:
Chung-Ho Chen, Arun K. Somani, "Architecture Technique Trade-Offs Using Mean Memory Delay Time," IEEE Transactions on Computers, vol. 45, no. 10, pp. 1089-1100, Oct. 1996, doi:10.1109/12.543704
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