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| Haomin Wu, M.a. Perkowski, Xiaoqiang Zeng, Nan Zhuang, "Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation," IEEE Transactions on Computers, vol. 45, no. 9, pp. 1084-1088, September, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/12.537134, author = {Haomin Wu and M.a. Perkowski and Xiaoqiang Zeng and Nan Zhuang}, title = {Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {9}, issn = {0018-9340}, year = {1996}, pages = {1084-1088}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.537134}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Generalized Partially-Mixed-Polarity Reed-Muller Expansion and Its Fast Computation IS - 9 SN - 0018-9340 SP1084 EP1088 EPD - 1084-1088 A1 - Haomin Wu, A1 - M.a. Perkowski, A1 - Xiaoqiang Zeng, A1 - Nan Zhuang, PY - 1996 KW - RM expansion KW - fixed-polarity RM expansion KW - Kronecker RM expansion KW - ESOP minimization KW - Gray code. VL - 45 JA - IEEE Transactions on Computers ER - | |||
Abstract—Generalized Partially-Mixed-Polarity Reed-Muller (GPMPRM) expansion, a canonical subfamily of Exclusive Sum of Products (ESOP), is presented. An efficient algorithm in two-dimensional data flow is proposed for computation of the GPMPRM forms. MCNC benchmark experimental results show that the minimal GPMPRM forms of these functions, on the average, have similar number of terms to their Sum of Products (SOP) counterparts while there are many functions for which the GPMPRM circuits are much smaller.
[1] R.K. Brayton, G.D. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincintelli, Logic Minimization Algorithms for VLSI Synthesis.Boston: Kluwer Academic, 1984.
[2] T. Sasao and P. Besslich, “On the Complexity of mod-2 Sum PLA's,” IEEE Trans. Computers, vol. 39, no. 2, pp. 262-266, Feb. 1990.
[3] T. Sasao, Logic Synthesis and Optimization. Kluwer Academic, 1993.
[4] V. Kebschull and W. Rosenstiel, "Efficient Graph-Based Computation and Manipulation of Functional Decision Diagrams," Proc. EDAC, pp. 278-282, 1993.
[5] M.A. Perkowski and M. Chrzanowska-Jeske, "An Exact Algorithm to Minimize Mixed-Radix Exclusive Sums of Products for Incompletely Specified Boolean Functions," Proc. IEEE ISCAS, pp. 1,652-1,655, 1990.
[6] D.H. Green, "Families of Reed-Muller Canonical Forms," Int'l J. Electronics, vol. 70, pp. 259-280, 1991.
[7] M. Davio, J.P. Deschamps, and A. Thayse, Discrete and Switching Functions.New York: McGraw-Hill, 1978.
[8] S.M. Reddy, "Easily Testable Realizations for Logic Functions," IEEE Trans. Computers, vol. 21, pp. 1,183-1,188, Nov. 1972.
[9] A. Sarabi and M.A. Perkowski, "Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/EXOR Canonical Networks," Proc. 29th ACM/IEEE DAC, pp. 30-35, 1992.
[10] Y.Z. Zhang and P.J.W. Rayner, "Minimization of Reed-Muller Polynomials with Fixed Polarity," IEE Proc., vol. 131, part E, pp. 177-186, Sept. 1984.
[11] P.K. Lui and J.C. Muzio,“Boolean matrix transforms for the minimization of modulo-2 canonical expansions,” IEEE Trans. Computers, vol. 41, no. 3, pp. 343-347, Mar. 1992.
[12] D.H. Green, "Reed-Muller Canonical Forms with Mixed Polarity and Their Manipulations," IEE Proc., vol. 137, part E, pp. 103-113, Jan. 1990.
[13] M. Cohn, "Inconsistent Canonical Forms of Switching Functions," IRE Trans. Electronic Computers, vol. 11, pp. 284-285, 1962.
[14] A. Mukhopadhyay and G. Schmitz, "Minimization of Exclusive OR and Logic Equivalence Switching Circuits," IEEE Trans. Computers, vol. 19, pp. 132-140, Feb. 1970.
[15] J.P. Robinson and C.L. Yeh, "A Method for Modulo-2 Minimization," IEEE Trans. Computers, vol. 31, no. 8, pp. 800-801, Aug. 1982.
[16] K.K. Saluja and S.M. Reddy, "Fault Detecting Test Sets for Reed-Muller Canonic Networks," IEEE Trans. Computers, vol. 24, pp. 995-998, Oct. 1975.
[17] S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 Technical Report," Microelectronics Center of North Carolina, Jan. 1991.

