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| Elisardo Antelo, Javier D. Bruguera, Emilio L. Zapata, "Unified Mixed Radix 2-4 Redundant CORDIC Processor," IEEE Transactions on Computers, vol. 45, no. 9, pp. 1068-1073, September, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/12.537131, author = {Elisardo Antelo and Javier D. Bruguera and Emilio L. Zapata}, title = {Unified Mixed Radix 2-4 Redundant CORDIC Processor}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {9}, issn = {0018-9340}, year = {1996}, pages = {1068-1073}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.537131}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Unified Mixed Radix 2-4 Redundant CORDIC Processor IS - 9 SN - 0018-9340 SP1068 EP1073 EPD - 1068-1073 A1 - Elisardo Antelo, A1 - Javier D. Bruguera, A1 - Emilio L. Zapata, PY - 1996 KW - High speed processor KW - elementary functions KW - pipelined design KW - redundant arithmetic KW - unified CORDIC algorithm. VL - 45 JA - IEEE Transactions on Computers ER - | |||
Abstract—We present a unified mixed radix CORDIC algorithm with carry-save arithmetic with a constant scale factor. The pipelined architecture of the processor is determined by a unique sequence of microrotations for the two modes of operation (rotation and vectoring) in circular and hyperbolic coordinates. The combination of radix-2 and radix-4 microrotations allows us to reduce the latency and size of the pipeline significantly. The unified algorithm is based on the correcting microrotation method, which we have extended to the vectoring mode in hyperbolic coordinates. We have also generalized the use of radix-4 microrotations to the two operation modes and coordinate systems.
[1] H.M. Ahmed, J.M. Delsome, and M. Morf, "Highly Concurrent Computing Structures for Matrix Arithmetic and Signal Processing, Computer, pp. 65-82, Jan. 1982.
[2] J.D. Bruguera, E. Antelo, and E.L. Zapata, "Design of a Pipelined Radix 4 CORDIC Processor," J. Parallel Computing, vol. 19, no. 7, pp. 729-744, 1993.
[3] J.R. Cacallaro and F.T. Luk,"CORDIC Arithmetic for a SVD Processor," J. Parallel and Distributed Computing, vol. 5, pp. 271-290, 1988.
[4] H. Dawid and H. Meyr,"High Speed Bit-Level Pipelined Architectures for Redundant CORDIC Implementation," Proc. Int'l Conf. Application Specific Array Processors, pp. 358-372,Oakland, Calif., IEEE CS Press, Aug. 1992.
[5] A.M. Despain, "Fourier Transform Computers Using CORDIC Iterations," IEEE Trans. Computers, vol. 23, pp. 993-1,001, Oct. 1974.
[6] J. Duprat and J.-M Muller,"The CORDIC Algorithm: New Results for Fast VLSI Implemenation," IEEE Trans. Computers, vol. 42, no. 2, pp. 168-178 Feb. 1993.
[7] M.D. Ercegovac and T. Lang,"Redundant and On-Line CORDIC: Application to Matrix Triangularisation and SVD," IEEE Trans. Computers, vol. 38, no. 6 pp. 725-740, June 1990.
[8] M.D. Ercegovac and T. Lang,“Simple radix-4 division with operands scaling,” IEEE Trans. Computers, vol. 39, no. 9, pp. 1,204-1,207, Sept. 1990.
[9] M.D. Ercegovac and T. Lang, Division and Square Root—Digit-Recurrence Algorithms and Implementations. Kluwer Academic, 1994.
[10] Y.M. Hu, “CORDIC-Based VLSI Architectures for Digital Signal Processing,” IEEE Signal Processing Magazine, vol. 9, pp. 16-35, 1992.
[11] K. Kota and J.R. Cavallaro,“Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors,” IEEE Trans. Computers, vol. 42, no. 7, pp. 769-779, July 1993.
[12] J. Lee and T. Lang,"Constant-Factor Redundant CORDIC for Angle Calculation and Rotation," IEEE Trans. Computers, vol. 41, no. 8, pp. 1,016-1,035, Aug. 1992.
[13] T. Noll,"Carry-Svae Architectures for High-Speed Digital Signal Processing," J. VLSI Signal Processing, vol. 3, pp. 121-140, June 1991.
[14] N. Takagi,T. Asada, and S. Yajima,"Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation," IEEE Trans. Computers, vol. 40, no. 9, pp. 989-995, Sept. 1991.
[15] D. Timmermann, H. Hahn, and B.J. Hosticka, "Low Latency Time CORDIC Algorithms," IEEE Trans. Computers, vol. 41, no. 8, pp. 1,010-1,015, Aug. 1992.
[16] J.E. Volder, "The CORDIC Trigonometric Computing Technique," IRE Trans. Electronic Computers, vol. 8, pp. 330-334, Sept. 1959.
[17] J.S. Walther, "A Unified Algorithm for Elementary Functions," Proc. Spring. Joint Computing Conf., pp. 379-385, 1971.

