This Article 
 Bibliographic References 
 Add to: 
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
September 1996 (vol. 45 no. 9)
pp. 1031-1044

Abstract—Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delay-insensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute low-skew clock signals and carefully balance propagation delays. However, unlike other methodologies that avoid clocks, phased logic supports the cyclic, deterministic behavior of the synchronous design paradigm. This permits the designer to rely chiefly on current experience and CAD tools to create phased logic systems. Marked graph theory is used as a framework for governing the interaction of phased logic gates that operate directly on Level-Encoded two-phase Dual-Rail (LEDR) signals. A synthesis algorithm is developed for converting clocked systems to phased logic systems and is applied to benchmark examples. Performance results indicate that phased logic tends to be tolerant of logic delay imbalances and has predictable worst-case timing behavior. Although phased logic requires additional circuitry, it has the potential to shorten the design cycle by reducing timing complexities.

[1] D. Smith, "Delving into Deep Submicron," Integrated System Design, pp. 15-22, Feb. 1995.
[2] R. Goering, "EDA&ASICs: Coping with Complexity," Electronic Eng. Times, pp. 49, 72, Oct.24, 1994.
[3] M.W. Garrett and M. Vetterli, “Joint Source/Channel Coding of Statistically Multiplexed Real-Time Services on Packet Networks,” IEEE/ACM Trans. Networking, vol. 1, no. 1, pp. 71-80, Feb. 1993.
[4] Self-Timed Control of Concurrent Processes, V.F. Varshavsky, ed. Boston: Kluwer Academic, 1990.
[5] L. Lavagno and A. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits, Kluwer Academic Publishers, Boston, 1993.
[6] I. David, R. Ginosar, and M. Yoeli, "Implementing Sequential Machines as Self-Timed Circuits," IEEE Trans. Computers, vol. 41, no. 1, pp. 12-17, Jan. 1992.
[7] I. Sutherland, "Micropipelines," Comm. ACM, Vol. 32 No. 6, ACM Press, New York, June 1989.
[8] M.E. Dean, T.E. Williams, and D.L. Dill, "Efficient Self-Timing with Level-Encoded 2-Phase Dual-Rail (LEDR)," Advanced Research in VLSI, pp. 55-70,Cambridge, Mass., 1991.
[9] R.E. Miller, Switching Theory Volume II: Sequential Circuits and Machines.New York: John Wiley&Sons, 1965.
[10] C.L. Seitz, "System Timing," Introduction to VLSI Systems, C. Mead and L. Conway, eds., pp. 218-262.Reading, Mass.: Addison-Wesley, 1980.
[11] T. Murata, “Petri Nets: Properties, Analysis and Application,” Proc. IEEE, vol. 77, no. 4, 1989.
[12] T.-A. Chu, "Synthesis of Self-timed VLSI Circuits from Graph-theoretic Specifications," Proc. Int'l Conf. Computer Design, pp. 220-223, 1987.
[13] T.H.-Y. Meng, R.W. Brodersen, and D.G. Messerschmitt, "Automatic Synthesis of Asynchronous Circuits from High-Level Specifications," IEEE Trans. Computer-Aided Design, vol. 8, pp. 1,185-1,205, Nov. 1989.
[14] L. Lavagno,K. Keutzer,, and A. Sangiovanni-Vincentelli,“Algorithms for synthesis of hazard-free asynchronous circuits,” 1991 Design Automation Conf., pp. 302-308, June 1991.
[15] A.J. McAuley, "Four State Asynchronous Architectures," IEEE Trans. Computers, vol. 41, no. 2, pp. 129-142, Feb. 1992.
[16] A.J. Martin, "The Limitations to Delay-Insensitivity in Asynchronous Circuits," Beauty Is Our Business: A Birthday Salute to Edsger W. Dijkstra, W.H.J. Feijen, D. Gries, A.J.M. van Gasteren and J.Misra, eds., pp. 302-311.New York: Springer-Verlag, 1990.
[17] J.A. Brzozowski and J.C. Ebergen, On the Delay-Sensitivity of Gate Networks IEEE Trans. Computers, vol. 41. no. 11, pp. 1349-1360, Nov. 1992.
[18] J.A. Brzozowski and J.C. Ebergen, "Recent Developments in the Design of Asynchronous Circuits," Proc. Int'l Conf. Fundamentals of Computation Theory, pp. 78-94, 1989.
[19] J.T. Udding, "A Formal Model for Defining and Classifying Delay-Insensitive Circuits and Systems," Distributed Computing, vol. 1, pp. 197-204, Oct. 1986.
[20] J.B. Dennis, "Data Flow Supercomputers," Computer, vol. 13, no. 11, pp. 48-56, Nov. 1980.
[21] F. Commoner, A.W. Holt, S. Even, and A. Pnueli, "Marked Directed Graphs," J. Computer and System Sciences, vol. 5, pp. 511-523, 1971.
[22] J.R. Jump and P.S. Thiagarajan, "On the Interconnection of Asynchronous Control Structures," J. ACM, vol. 22, pp. 596-612, Oct. 1975.
[23] S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide Version 3.0," Microelectronics Center of N.C., Jan. 1991.
[24] C.D. Nielsen and M. Kishinevsky, "Performance Analysis Based on Timing Simulation," Proc. Design Automation Conf., pp. 70-76, 1994.
[25] F. Baccelli, G. Cohen, G.J. Olsder, and J.-P. Quadrat, Synchronization and Linearity: An Algebra for Discrete Event Systems.New York: John Wiley&Sons, 1992.
[26] H.P. Hillion and J.-M. Proth, "Performance Evaluation of Job-Shop Systems Using Timed Event-Graphs," IEEE Trans. Automatic Control, vol. 34, pp. 3-9, Jan. 1989.
[27] R. Auletta, B. Reese, and C. Traver, "A Comparison of Synchronous and Asynchronous FSMD Designs," Proc. Int'l Conf. Computer Design, pp. 178-182, 1993.
[28] B. Lin and H. De Man, "Low-Power Driven Technology Mapping Under Timing Constraints," Proc. Int'l Conf. Computer Design, pp. 421-427, 1993.
[29] T.G. Noll and E. De Man, "Pushing the Performance Limits due to Power Dissipation of Future ULSI Chips," Proc. Int'l Symp. Circuits and Systems, pp. 1,652-1,655, 1992.
[30] A. Ghosh et al., "Estimation of Average Switching Activity in Combinational and Sequential Circuits," Proc. 29th Design Automation Conf., IEEE CS Press, 1992, pp. 253-259.

Index Terms:
Asynchronous circuitry, data flow, delay-insensitive circuitry, dual-rail encoding, LEDR, marked graphs, phased logic, synchronous circuitry.
Daniel H. Linder, James C. Harden, "Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry," IEEE Transactions on Computers, vol. 45, no. 9, pp. 1031-1044, Sept. 1996, doi:10.1109/12.537126
Usage of this product signifies your acceptance of the Terms of Use.