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Issue No.09 - September (1996 vol.45)
pp: 1003-1016
ABSTRACT
<p><b>Abstract</b>—Design of Cellular Automata (CA) based byte error correcting code analogous to extended Reed-Solomon code has been proposed in [<ref rid="bibt10031" type="bib">1</ref>], [<ref rid="bibt10032" type="bib">2</ref>]. This code has same restrictions on error correction as that of extended R-S code. In this paper a new design scheme has been reported for parallel implementation of CA based S<it>b</it>EC/D<it>b</it>ED and D<it>b</it>EC/D<it>b</it>ED code that is analogous to the conventional R-S code. Both the encoder and decoder of this code can be efficiently implemented with an array of CA (CAA) with high throughput. The design is ideally suited for high speed memory systems built with byte organized RAM chips. Extension of the scheme to detect/correct larger number of byte errors has also been reported. Throughput of the decoder to handle <it>t</it> byte errors (<it>t</it>≤ 4) can be found to be substantially better than that of conventional R-S decoder. The proposed decoder provides a simple, modular and cost effective design that ideally suits for VLSI implementation.</p>
INDEX TERMS
Cellular automata, error correcting code, cellular automata array (CAA), error vector, error space.
CITATION
Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri, "CAA Decoder for Cellular Automata Based Byte Error Correcting Code", IEEE Transactions on Computers, vol.45, no. 9, pp. 1003-1016, September 1996, doi:10.1109/12.537123
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