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CAA Decoder for Cellular Automata Based Byte Error Correcting Code
September 1996 (vol. 45 no. 9)
pp. 1003-1016
ASCII Text
x 
 
Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri, "CAA Decoder for Cellular Automata Based Byte Error Correcting Code," IEEE Transactions on Computers, vol. 45, no. 9, pp. 1003-1016, September, 1996.
 
 
BibTex
x
 
@article{ 10.1109/12.537123,
author = {Koppolu Sasidhar and Santanu Chattopadhyay and Parimal Pal Chaudhuri},
title = {CAA Decoder for Cellular Automata Based Byte Error Correcting Code},
journal ={IEEE Transactions on Computers},
volume = {45},
number = {9},
issn = {0018-9340},
year = {1996},
pages = {1003-1016},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.537123},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - CAA Decoder for Cellular Automata Based Byte Error Correcting Code
IS - 9
SN - 0018-9340
SP1003
EP1016
EPD - 1003-1016
A1 - Koppolu Sasidhar,
A1 - Santanu Chattopadhyay,
A1 - Parimal Pal Chaudhuri,
PY - 1996
KW - Cellular automata
KW - error correcting code
KW - cellular automata array (CAA)
KW - error vector
KW - error space.
VL - 45
JA - IEEE Transactions on Computers
ER -
 

Abstract—Design of Cellular Automata (CA) based byte error correcting code analogous to extended Reed-Solomon code has been proposed in [1], [2]. This code has same restrictions on error correction as that of extended R-S code. In this paper a new design scheme has been reported for parallel implementation of CA based SbEC/DbED and DbEC/DbED code that is analogous to the conventional R-S code. Both the encoder and decoder of this code can be efficiently implemented with an array of CA (CAA) with high throughput. The design is ideally suited for high speed memory systems built with byte organized RAM chips. Extension of the scheme to detect/correct larger number of byte errors has also been reported. Throughput of the decoder to handle t byte errors (t≤ 4) can be found to be substantially better than that of conventional R-S decoder. The proposed decoder provides a simple, modular and cost effective design that ideally suits for VLSI implementation.

[1] D. Roy Chowdhury, I. Sen Gupta, and P. Pal Chaudhuri, "Cellular Automata Based Byte Error Correcting Code," IEEE Trans. Computers, vol. 44, no. 3, pp. 371-382, Mar. 1995.
[2] D. Roy Chowdhury and P. Pal Chaudhuri, "Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders," Proc. VLSI Design '94, pp. 283-286, July 1982.
[3] S. Kaneda and E. Fujiwara, "Single Byte Error Correcting-Double Byte Error Detecting Codes for Memory Systems," IEEE Trans. Computers, vol. 31, no. 7, pp. 596-602, July 1982.
[4] K.Y. Liu, "Architecture Design for VLSI Design of RS Decoders," IEEE Trans. Computers, vol. 33, Feb. 1984.
[5] H. Shao, "A VLSI Design of a Pipelined Reed-Solomon Decoder," IEEE Trans. Computers, vol. 34, no. 5, pp. 393-403, May 1985.
[6] H. Okano and H. Imai, "A Construction Method of High Speed Decoders Using ROM's for BCH and RS Codes," IEEE Trans. Computers, vol. 36, no. 10, Oct. 1987.
[7] A.K. Das and P. Pal Chaudhuri, "Efficient Characterization of Cellular Automata," Proc. IEE (Part E), vol. 137, pp. 81-87, Jan. 1990.
[8] A.K. Das, D. Saha, A.R. Chowdhury, S. Misra, and P. Pal Chaudhuri, "Signature Analyzer Based on Additive Cellular Automata," Proc. 20th Fault Tolerant Computing Systems, pp. 265-272,U.K., June 1990.
[9] P.D. Hortensius et al., "Cellular Automata Based Pseudo-Random Number Generators for Built-In Self-Test," IEEE Trans. Computer-Aided Design, vol. 8, pp. 842-859, Aug. 1989.
[10] W. Pries, A. Thanailakis, and H.C. Card, "Group Properties of Cellular Automata and VLSI Applications," IEEE Trans. Computers, vol. 35, no. 12, pp. 1,013-1,024, Dec. 1986.
[11] M. Serra et al., "The Analysis of One-Dimensional Linear Cellular Automata and Their Aliasing Properties," IEEE Trans. Computer-Aided Design, vol. 9, no. 7, pp. 767-778, July 1990.
[12] A. Das and P.P. Chaudhuri, “Pseudo-Exhaustive Test Pattern Generation Using Cellular Automata,” IEEE Trans. Computers, Vol. 42, No. 3, Mar. 1993, pp. 340-352.
[13] S. Nandi, B.K. Kar, and P. Pal Chaudhuri, "Theory and Application of Cellular Automata in Cryptography," IEEE Trans. Computers, vol. 43, no. 12, pp. 1,346-1,357, Dec. 1994.
[14] D. Roy Chowdhury, S. Basu, I. Sen Gupta, and P. Pal Chaudhuri, "Design of CAECC—Cellular Automata Based Error Correcting code," IEEE Trans. Computers, vol. 43, no. 6, pp. 759-764, June 1994.
[15] O. Martin, A.M. Odlyzko, and S. Wolfram, "Algebraic Properties of Cellular Automata," Comm. Math. Phys., vol. 93, pp. 219-258, 1984.
[16] P.D. Hortensius, R.D. McLeod, and H.C. Card, "Cellular Automata Based Signature Analysis for Built-In Self-Test," IEEE Trans. Computers, vol. 39, no. 10, pp. 1,273-1,283, Oct. 1990.
[17] W. Press, B. Flannery, S. Teukolsky, and W. Vetterling, "Numerical Recipes. Cambridge Univ. Press, 1986.
[18] T.R.N. Rao and Fujiwara, Error-Coding for Computer Systems.Englewood Cliffs, N.J.: Prentice Hall, 1989.

Index Terms:
Cellular automata, error correcting code, cellular automata array (CAA), error vector, error space.
Citation:
Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri, "CAA Decoder for Cellular Automata Based Byte Error Correcting Code," IEEE Transactions on Computers, vol. 45, no. 9, pp. 1003-1016, Sept. 1996, doi:10.1109/12.537123
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