Issue No.08 - August (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.536242
<p><b>Abstract</b>—Multilevel Logic Optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A sufficient condition for a multilevel unate circuit to be "hazard free delay fault testable" is presented. In contrast to existing results that consider either "single path propagating hazard free robust tests" or "general robust tests" we consider "multiple path propagating hazard free robust tests" in our analysis.</p>
Delay fault testable circuits, logic optimization, robust tests, testability enhancing transformations, testability preserving transformations.
Sreejit Chakravarty, "A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits", IEEE Transactions on Computers, vol.45, no. 8, pp. 985-991, August 1996, doi:10.1109/12.536242