This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Augmented Binary Hypercube: A New Architecture for Processor Management
August 1996 (vol. 45 no. 8)
pp. 980-984

Abstract—Augmented Binary Hypercube (AH) architecture consists of the binary hypercube processor nodes (PNs) and a hierarchy of management nodes (MNs). Several distributed algorithms maintain subcube information at the MNs to realize fault tolerant, fragmentation free processor allocation and load balancing. For efficient implementation of AH, we map MNs onto PNs, define and prove infeasibility of ideal mappings. We propose easily implementable non-optimal mappings, having negligible overheads on performance. Extensive simulation studies and performance analysis conclude that these algorithms realize significantly better average job completion time and higher processor utilization, as compared to the best sequential allocation schemes and parallel implementation of Free List [7]. AH algorithms can be tuned or adapt to the job and system characteristics, and resource management traffic.

[1] I. Ahmad, A. Ghafoor, and G.C. Fox, "Hierarchical Scheduling of Dynamic Parallel Computation on Hypercube Multicomputers," J. Parallel and Distributed Computing, vol. 20, no. 3, pp. 317-329, Mar. 1994.
[2] M. S. Chen and K. G. Shin,“Processor allocation in an$N$-cube multiprocessor using gray codes,”IEEE Trans. Comput., vol. C-37, pp. 1396–1407, Dec. 1987.
[3] P.-J. Chuang and N.-F. Tzeng,"A Fast Recognition-Complete Processor Allocation Strategy for Hypercube Computers," IEEE Trans. Computers, pp. 467-479, Apr. 1992.
[4] W.J. Dally, "Virtual-Channel Flow Control," IEEE Trans. Parallel and Distributed Systems, vol. 3, no. 2, pp. 194-205, Mar. 1992.
[5] S. Dutt and J.P. Hayes, "Subcube Allocation in Hypercube Computers," IEEE Trans. Computers, vol. 40, no. 3, pp. 341-352, Mar. 1991.
[6] P.T. Gaughan and S. Yalamanchili, “Adaptive Routing Protocols for Hypercube Interconnection Networks,” Computer, vol. 26, no. 5, pp. 12–23, May 1993.
[7] J. Kim, C.R. Das, and W. Lin, "A Processor Allocation Scheme for Hypercube Computers," Proc. 1989 Int'l Conf. Parallel Processing, vol. 2, pp. 231-238, Aug. 1989.
[8] D.W. Krumme, K.N. Venkataraman, and G. Cybenko, "Hypercube Embedding is NP-Complete," Proc. Hypercube Multiprocessors 1986, PA: SIAM 1986, pp. 148-157, 1986.
[9] H.K.B. Lalgudi, I.F. Akyildiz, and S. Yalamanchili, "Augmented Binary Hypercube: A New Architecture for Processor Management in Binary Hypercubes," TR-GIT/CSRL-93/03, pp. 27-34, Mar. 1993.
[10] D.D. Sharma and D.K. Pradhan, "Fast and Efficient Strategies for Cubic and Noncubic Allocation in Hypercube Multiprocessors," Proc. Int'l Conf. Parallel Processing, pp. 118-127, 1993.
[11] Q. Yang and H. Wang, "A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors," IEEE Trans. Parallel and Distributed Systems, vol. 4, pp. 1,165-1,171, Oct. 1993.

Index Terms:
Augmented binary hypercube, update algorithms, ideal mapping, resource management traffic.
Citation:
Hari Lalgudi, Ian F. Akyildiz, Sudhakar Yalamanchili, "Augmented Binary Hypercube: A New Architecture for Processor Management," IEEE Transactions on Computers, vol. 45, no. 8, pp. 980-984, Aug. 1996, doi:10.1109/12.536241
Usage of this product signifies your acceptance of the Terms of Use.