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System Dependability Evaluation via a Fault List Generation Algorithm
August 1996 (vol. 45 no. 8)
pp. 974-979

Abstract—The size and complexity of modern dependable computing systems has significantly compromised the ability to accurately measure system dependability attributes such as fault coverage and fault latency. Fault injection is one approach for the evaluation of dependability metrics. Unfortunately, fault injection techniques are difficult to apply because the size of the fault set is essentially infinite. Current techniques select faults randomly resulting in many fault injection experiments which do not yield any useful information. This research effort has developed a new deterministic, automated dependability evaluation technique using fault injection. The primary objective of this research effort was the development and implementation of algorithms which generate a fault set which fully exercises the fault detection and fault processing aspects of the system. The theory supporting the developed algorithms is presented first. Next, a conceptual overview of the developed algorithms is followed by the implementation details of the algorithms. The last section of this paper presents experimental results gathered via simulation-based fault injection of an Interlocking Control System (ICS). The end result is a deterministic, automated method for accurately evaluating complex dependable computing systems using fault injection.

[1] J. Arlat, Y. Crouzet, and J.-C. Laprie, “Fault Injection for Dependability Validation of Fault-Tolerant Computing Systems,” Proc. IEEE Int'l Symp. Fault-Tolerant Computing, pp. 348–355, 1989.
[2] J.H. Lala, "Fault Detection, Isolation and Reconfiguration in FTMP: Methods and Experimental Results," Proc. Fifth AIAA/IEEE Digital Avionics Systems Conf., pp. 21.3.1-21.3.9, 1983.
[3] J. Karlsson et al., “Two Fault‐Injection Techniques for Test of Fault‐Handling Mechanisms,” Proc. Int’l Test Conf., IEEE CS Press, Los Alamitos, Calif., Order No. 2156, 1991, pp. 140‐149.
[4] Z. Segall et al., “FIAT—Fault Injection Based Automated Testing Environment,” Proc. IEEE Int'l Symp. Fault-Tolerant Computing, pp. 102–107, 1988.
[5] G. Kanawati, N. Kanawati, and J. Abraham, “FERRARI: A Tool for the Validation of System Dependability Properties,” Proc. IEEE Int'l Symp. Fault-Tolerant Computing, pp. 336–344, 1992.
[6] R. Chillarege and N.S. Bowen, “Understanding Large System Failures—A Fault Injection Experiment,” Proc. IEEE Int'l Symp. Fault-Tolerant Computing, pp. 356–363, June 1989.
[7] G.S. Choi, R.K. Iyer, and V.A. Carreno, "Simulated Fault Injection: A Methodology to Evaluate Fault Tolerant Microprocessor Architectures," IEEE Trans. Reliability, vol. 39, no. 4, pp. 486-491, Oct. 1990.
[8] S. Kim and R.K. Iyer, "Impact of Device Level Faults in a Digital Avionic Processor," Proc. AIAA/IEEE Eighth Digital Avionics Systems Conf., pp. 428-435, Oct. 1988.
[9] J.G. McGough, F.L. Swern, and S. Bavuso, "New Results in Fault Latency Modeling," Proc. IEEE Eascon Conf. pp. 299-306, Aug. 1983.
[10] M. Ball and F. Hardie, "Effects and Detection of Intermittent Failures in Digital Ssystems," Proc. AFIPS Fall Joint Computer Conf., pp. 329-335, 1969.
[11] D. Lomelino and R.K. Iyer, "Error Propagation in a Digital Avionic Processor," Proc. Real Time Systems Symp., pp. 218-225, 1986.
[12] R.L. Baker, L.S. Mangum, and C.O. Scheper, "A Simulation-Based Fault Injection Experiment to Evaluate Self-Test Diagnostics for a Fault-Tolerant Computer," Proc. AIAA/IEEE Eighth Digital Avionics Systems Conf., pp. 220-226, Oct. 1988.
[13] T.A. Delong, "Performance and Safety Analysis of a Microprocessor-based Embedded Control System using VHDL," MS thesis, Univ. of Virginia, 1993.
[14] R.K. Iyer and D.J. Rossetti, "A Measurement-Based Model for Workload Dependence of CPU Errors," IEEE Trans. Computers, vol. 35, no. 6, pp. 511-519, June 1986.
[15] R.K. Iyer and P. Velardi, "Hardware-Related Software Errors: Measurement and Analysis," IEEE Trans. Software Eng., vol. 11, no. 2, pp. 223-231, Feb. 1985,.
[16] D.T. Smith, B.W. Johnson, and J.A. Profeta, "A Malicious Fault List Generation Algorithm for the Evaluation of System Coverage," Reliability and Maintainability Symp., Jan. 1995.
[17] D.T. Smith, "A Malicious Fault List Generation Algorithm for the Evaluation of System Coverage," doctoral thesis, Dept. Electrical Engineering, Univ. of Virginia, 1993.
[18] M.H. Salinas, B.W. Johnson, and J.H. Aylor, "Implementation Independent Model of an Instruction Set Architecture in VHDL," IEEE Design&Test of Computers, vol. 10, no. 3, pp. 42-54, Sept. 1993.
[19] S.M. Thatte and J.A. Abraham, "Test Generation for Microprocessors," IEEE Trans. Computers, vol. 29, no. 6, pp. 429-441, June 1980.
[20] L. Shen and S.Y.H. Su, "A Functional Testing Method for Microprocessors," Proc. 14th Int'l Symp. Fault-Tolerant Computing, pp. 212-218, 1984.

Index Terms:
Fault injection, error injection, latency, simulation, VHDL.
Citation:
D. Todd Smith, Barry W. Johnson, Joseph A. Profeta III, "System Dependability Evaluation via a Fault List Generation Algorithm," IEEE Transactions on Computers, vol. 45, no. 8, pp. 974-979, Aug. 1996, doi:10.1109/12.536240
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