Issue No.08 - August (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.536239
<p><b>Abstract</b>—This paper modifies the tree RAM (TRAM) architecture[<ref rid="bibt09691" type="bib">1</ref>] of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yeild for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture.</p>
Access time, built-in testing, modified TRAM, multimegabit RAM, pattern sensitive faults, yield.
S. Rai, V.p. Kirpalani, "A Modified TRAM Architecture", IEEE Transactions on Computers, vol.45, no. 8, pp. 969-974, August 1996, doi:10.1109/12.536239