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A Modified TRAM Architecture
August 1996 (vol. 45 no. 8)
pp. 969-974

Abstract—This paper modifies the tree RAM (TRAM) architecture[1] of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yeild for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture.

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Index Terms:
Access time, built-in testing, modified TRAM, multimegabit RAM, pattern sensitive faults, yield.
S. Rai, V.p. Kirpalani, "A Modified TRAM Architecture," IEEE Transactions on Computers, vol. 45, no. 8, pp. 969-974, Aug. 1996, doi:10.1109/12.536239
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