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| S. Rai, V.p. Kirpalani, "A Modified TRAM Architecture," IEEE Transactions on Computers, vol. 45, no. 8, pp. 969-974, August, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/12.536239, author = {S. Rai and V.p. Kirpalani}, title = {A Modified TRAM Architecture}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {8}, issn = {0018-9340}, year = {1996}, pages = {969-974}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.536239}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A Modified TRAM Architecture IS - 8 SN - 0018-9340 SP969 EP974 EPD - 969-974 A1 - S. Rai, A1 - V.p. Kirpalani, PY - 1996 KW - Access time KW - built-in testing KW - modified TRAM KW - multimegabit RAM KW - pattern sensitive faults KW - yield. VL - 45 JA - IEEE Transactions on Computers ER - | |||
Abstract—This paper modifies the tree RAM (TRAM) architecture[1] of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yeild for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture.
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