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A Modified TRAM Architecture
August 1996 (vol. 45 no. 8)
pp. 969-974

Abstract—This paper modifies the tree RAM (TRAM) architecture[1] of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yeild for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture.

[1] N.T. Jarwala and D.K. Pradhan, "TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAMs," IEEE Trans. Computers, vol. 37, no. 10, pp. 1,235-1,250, Oct. 1988.
[2] H.S. Stone, High Performance Computer Architecture.Reading, Mass: Addison Wesley, 1993.
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[5] A.V. Ferris-Prabhu, Introduction to Semiconductor Device Yield Modeling.London: Artech House, 1992.
[6] V.P. Kirpalani, "Modified TRAM: A Design Methodology for High Performance, Easily Testable Multimegabit RAM," M.S. Thesis, Dept. of Electrical Eng., Louisiana State Univ., Sept. 1993.
[7] P. Mazumder and J.H. Patel, Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories IEEE Trans. Computers, vol. 38, no. 3, pp. 394-407, Mar. 1989.
[8] H. Koike, T. Takeshima, and M. Takada, "A BIST Scheme Using Micro Program ROM for Large Capacity Memories," Proc. IEEE Int'l Test Conf., pp. 815-822, 1990.
[9] A. Van de Goor, Testing Semiconductor Memories, John Wiley&Sons, New York, 1991.
[10] M. Franklin and K.K. Saluja, "An Algorithm to Test RAMS for Physical Neighborhood Pattern Sensitive Faults," Proc. IEEE Int'l Test Conf., pp. 675-684, 1991.

Index Terms:
Access time, built-in testing, modified TRAM, multimegabit RAM, pattern sensitive faults, yield.
Citation:
S. Rai, V.p. Kirpalani, "A Modified TRAM Architecture," IEEE Transactions on Computers, vol. 45, no. 8, pp. 969-974, Aug. 1996, doi:10.1109/12.536239
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