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Issue No.08 - August (1996 vol.45)
pp: 939-949
ABSTRACT
<p><b>Abstract</b>—Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose processors. The resultant test patterns, generated by continuously accumulating a constant value, provide a complete state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme [<ref rid="bibt093919" type="bib">19</ref>] facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and no area overhead.</p>
INDEX TERMS
Accumulators, arithmetic generators, built-in self-test, data-path architectures, pseudo-exhaustive generators, state coverage.
CITATION
Janusz Rajski, Sanjay Gupta, "Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns", IEEE Transactions on Computers, vol.45, no. 8, pp. 939-949, August 1996, doi:10.1109/12.536236
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