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IEEE Transactions on Computers
August 1996 (vol. 45 no. 8)
ISSN: 0018-9340
Table of Contents
Editor's Note
Editor's Note
(Abstract)
pp. 865-867
ABSTRACT
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PAPERS
The Effect of Program Behavior on Fault Observability
(Abstract)
Nicholas S. Bowen
Dhiraj K. Pradhan
pp. 868-880
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A Methodology for the Rapid Injection of Transient Hardware Errors
(Abstract)
Charles R. Yount
Daniel P. Siewiorek
pp. 881-891
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On Diagnosability of Large Fault Sets in Regular Topology-Based Computer Systems
(Abstract)
Arun K. Somani
Ofer Peleg
pp. 892-903
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On Evaluating and Optimizing Weights for Weighted Random Pattern Testing
(Abstract)
Amitava Majumdar
pp. 904-916
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A Sweeping Line Approach to Interconnect Testing
(Abstract)
Jose Salinas
Yinan Shen
Fabrizio Lombardi
pp. 917-929
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Reducing the MISR Size
(Abstract)
Jacob Savir
pp. 930-938
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Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
(Abstract)
Sanjay Gupta
Janusz Rajski
Jerzy Tyszer
pp. 939-949
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Testability of Convergent Tree Circuits
(Abstract)
R.D. (Shawn) Blanton
John P. Hayes
pp. 950-963
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BRIEF CONTRIBUTIONS
Optimal Realization of Sets of Interconnection Functions on Synchronous Multiple Bus Systems
(Abstract)
Priyalal Kulasinghe
Ahmed El-Amawy
pp. 964-969
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A Modified TRAM Architecture
(Abstract)
S. Rai
V.p. Kirpalani
pp. 969-974
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System Dependability Evaluation via a Fault List Generation Algorithm
(Abstract)
D. Todd Smith
Barry W. Johnson
Joseph A. Profeta III
pp. 974-979
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Augmented Binary Hypercube: A New Architecture for Processor Management
(Abstract)
Hari Lalgudi
Ian F. Akyildiz
Sudhakar Yalamanchili
pp. 980-984
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A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits
(Abstract)
Sreejit Chakravarty
pp. 985-991
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