Publication 1996 Issue No. 7 - July Abstract - A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields
A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields
July 1996 (vol. 45 no. 7)
pp. 856-861
 ASCII Text x Christof Paar, "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields," IEEE Transactions on Computers, vol. 45, no. 7, pp. 856-861, July, 1996.
 BibTex x @article{ 10.1109/12.508323,author = {Christof Paar},title = {A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields},journal ={IEEE Transactions on Computers},volume = {45},number = {7},issn = {0018-9340},year = {1996},pages = {856-861},doi = {http://doi.ieeecomputersociety.org/10.1109/12.508323},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite FieldsIS - 7SN - 0018-9340SP856EP861EPD - 856-861A1 - Christof Paar, PY - 1996KW - Finite field multiplicationKW - bit parallel multiplicationKW - composite fieldsKW - polynomial multiplicationKW - Karatsuba Ofman algorithmKW - primitive polynomialsKW - VLSI architecture.VL - 45JA - IEEE Transactions on ComputersER -

Abstract—In this paper a new bit-parallel structure for a multiplier with low complexity in Galois fields is introduced. The multiplier operates over composite fields GF((2n)m), with k = nm. The Karatsuba-Ofman algorithm is investigated and applied to the multiplication of polynomials over GF(2n). It is shown that this operation has a complexity of order $O(k^{{\rm log}_23})$ under certain constraints regarding k. A complete set of primitive field polynomials for composite fields is provided which perform modulo reduction with low complexity. As a result, multipliers for fields GF(2k) up to k = 32 with low gate counts and low delays are listed. The architectures are highly modular and thus well suited for VLSI implementation.

[1] A. Odlyzko, "Discrete Logarithms in Finite Fields and Their Cryptographic Significance," Lecture Notes in Computer Science 209, pp. 224-316.Berlin: Springer-Verlag, 1984.
[2] R. Blahut, Theory and Practice of Error Control Codes.Reading, Mass.: Addison-Wesley, 1983.
[3] C.C. Wang,T.K. Truong,H.M. Shao,L.J. Deutsch,J.K. Omura, and I.S. Reed,"VLSI Architectures for Computing Multiplications and Inverses inGF(2m)," IEEE Trans. Computers, vol. 34, no. 8, pp. 709-716, Aug. 1985.
[4] T. Itoh and S. Tsujii, “Structure of Parallel Multipliers for a Class of Finite Fields$GF(2^m)$,” Information and Computation, vol. 83, pp. 21-40, 1989.
[5] E.D. Mastrovito,"VLSI Design for Multiplication over Finite Fields," LNCS-357, Proc. AAECC-6, pp. 297-309,Rome, July 1988, Springer-Verlag.
[6] M.A. Hasan, M. Wang, and V.K. Bhargava, Modular Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields$GF(2^m)$ IEEE Trans. Computers, vol. 41, no. 8, pp. 962-971, Aug. 1992.
[7] V. Afanasyev, "Complexity of VLSI Implementation of Finite Field Arithmetic," Proc. II. Int'l Workshop Algebraic and Combinatorial Coding Theory, pp. 6-7,Leningrad, USSR, Sept. 1990.
[8] V. Afanasyev, "On the Complexity of Finite Field Arithmetic," Proc. Fifth Joint Soviet-Swedish Int'l. Workshop Information Theory, pp. 9-12,Moscow, USSR, Jan. 1991.
[9] A. Pincin, "A New Algorithm for Multiplication in Finite Fields," IEEE Trans. Computers, vol. 38, no. 7, pp. 1,045-1,049, July 1989.
[10] D. Green and I. Taylor, "Irreducible Polynomials over Composite Galois Fields and Their Applications in Coding Techniques," Proc. IEE, vol. 121, pp. 935-939, Sept. 1974.
[11] J. Komo and M. Lam, "Primitive Polynomials and m-Sequences over GF(qm)," IEEE Trans. Information Theory, vol. 39, pp. 643-647, Mar. 1993.
[12] A. Karatsuba and Y. Ofman, "Multiplication of Multidigit Numbers on Automata," Sov. Phys.-Dokl. (Engl. transl.), vol. 7, no. 7, pp. 595-596, 1963.
[13] D. Knuth, The Art of Computer Programming, Vol. 2, Addison-Wesley, Reading, Mass., 1998.
[14] E. Mastrovito, "VLSI Architectures for Computation in Galois Fields," PhD thesis, Linköping Univ., Dept. of Electrical Eng., Linköping, Sweden, 1991.
[15] R. Fateman, "Polynomial Multiplication, Powers and Asymptotic Analysis: Some Comments," SIAM J. Computing, vol. 7, pp. 196-21, Sept. 1974.
[16] C. Paar, "Efficient VLSI Architectures for Bit-Parallel Computation in Galois Fields," PhD thesis, (English translation), Inst. for Experimental Mathematics, Univ. of Essen, Essen, Germany, June 1994.
[17] C. Paar and O. Hooijen, "Implementation of a Reprogrammable Reed-Solomon Decoder over GF(216) on a Digital Signal Processor with External Arithmetic Unit," Proc. Fourth Int'l ESA Workshop Digital Signal Processing Techniques Applied to Space Comm., King's College, London, Sept.26-28 1994.

Index Terms:
Finite field multiplication, bit parallel multiplication, composite fields, polynomial multiplication, Karatsuba Ofman algorithm, primitive polynomials, VLSI architecture.
Citation:
Christof Paar, "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields," IEEE Transactions on Computers, vol. 45, no. 7, pp. 856-861, July 1996, doi:10.1109/12.508323