This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Analysis of a Control Mechanism for a Variable Speed Processor
July 1996 (vol. 45 no. 7)
pp. 793-801

Abstract—One limitation on the operating speed of electronic circuits is the rate at which the packaging can dissipate heat. In CMOS technology, the heat generated by a processor is approximately proportional to its clock rate. This paper examines the idea of using a variable-speed processor (VSP) that can be operated at a high clock speed, and then slowed down to a lower speed before heat accumulation destroys the circuit. Under a workload consisting of bursts of work alternating with idle periods (corresponding to cache misses or other delays), this results in a higher average operating speed. This paper shows the optimality of a bang-bang control for the clock rate. It also examines an easier-to-implement policy that estimates the junction temperature through an upper bound, and uses this to control the clock rate. Closed-form expressions are derived for the mean rate of instructions executed by a VSP using each control method. Numerical studies show that both policies give substantial improvements in performance over a single speed processor. Furthermore, the studies suggest that a VSP with a maximum clock rate of 2-4 times that of the single speed processor would suffice to obtain the bulk of the performance improvement. In many cases, the average throughput gain is on the order of 40-60%, without exceeding thermal limits.

[1] H.B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Addison-Wesley Publishing Co., 1990.
[2] A. Chandrakasan, S. Sheng, and R. Brodersen, "Low-Power CMOS Digital Design," IEEE J. Solid-State Circuits, Apr. 1992, pp. 473-484.
[3] J. Circello et al., "The Superscalar Architecture of the MC68060," IEEE Micro, Apr. 1995.
[4] P. Horowitz and W. Hill, The Art of Electronics, 2nd ed., Cambridge Univ. Press, Cambridge, UK, 1989, pp. 222-223.
[5] Intel Corp. Intel486 DX Microprocessor Data Book, Oct. 1992. Order no. 240440-005.
[6] S. Karlin and H.M. Taylor, A First Course in Stochastic Processes. Academic Press Inc., 1975.
[7] C. Georgiou, T. Larsen, and E. Schenfeld, Variable Chip-Clocking Mechanism. U.S. Patent number 5,189,314, Feb.23, 1993.
[8] B.S. Siegal, "Thermal Characterization of Surface Mount Devices," Proc. Ninth IEEE Semiconductor Thermal Measurement and Management Symposium,Austin, TX, pp. 99-107, Feb. 1993.
[9] B.W. Suessmith and G. Paap III, "PowerPC 603 Microprocessor: Power Management," Comm. ACM, vol. 37, pp. 43-46, June 1994.
[10] R.R. Tummala and E.J. Rymaszewski eds., Microelectronics Packaging Handbook. Van Nostrand Reinhold, 1989.

Index Terms:
Variable speed processor, throughput gain, thermal modeling, performance analysis, Markov processes.
Citation:
Arif Merchant, Benjamin Melamed, Eugen Schenfeld, Bhaskar Sengupta, "Analysis of a Control Mechanism for a Variable Speed Processor," IEEE Transactions on Computers, vol. 45, no. 7, pp. 793-801, July 1996, doi:10.1109/12.508318
Usage of this product signifies your acceptance of the Terms of Use.