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Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines
July 1996 (vol. 45 no. 7)
pp. 769-781

Abstract—This paper reports some of the interesting properties and relationships of a nongroup Cellular Automata (CA) and its dual. A special class of nongroup Cellular Automata denoted as D1*CA is analytically investigated. Based on such analysis, D1*CA has been proposed as an ideal test machine which can be efficiently embedded in a finite state machine to enhance the testability of the synthesized design. A state encoding algorithm has been formulated to embed the D1*CA based test machine in the synthesized FSM while minimizing the hardware overhead. The unique state transition properties of D1*CA are then used in designing an easy testing scheme for the FSM. Experiments on FSM benchmarks have shown that the scheme achieves 100% coverage of all single stuck-at faults at the cost of hardware overhead and circuit delay that are comparable, if not better, to that incurred for scan path based designs. However, the major advantage of the scheme is the significant reduction of test time overhead due to integration of an embedded test machine in the design at the synthesis phase.

[1] V.D. Agarwal and K.T. Cheng, "Finite State Machine Synthesis with Embedded Test Function," J. Electronic Testing: Theory and Application, vol. 1, pp. 221-228, 1990.
[2] D. Roy Chowdhury, "Theory and Applications of Additive Cellular Automata for Reliable and Testable VLSI Circuit Design," PhD thesis, IIT, Kharagpur, India, 1992.
[3] D. Roy Chowdhury, S. Basu, I. Sen Gupta, and P. Pal Chaudhuri, "Design of CAECC—Cellular Automata Based Error Correcting code," IEEE Trans. Computers, vol. 43, no. 6, pp. 759-764, June 1994.
[4] D. Roy Chowdhury, I. Sen Gupta, and P. Pal Chaudhuri, "Cellular Automata Based Byte Error Correcting Code," IEEE Trans. Computers, vol. 44, no. 3, pp. 371-382, Mar. 1995.
[5] D. Roy Chowdhury, S. Chakraborty, B. Vamsi, and P. Pal Chaudhuri, "Cellular Automata Based Synthesis of Easily and Fully Testable FSMs," Proc. ICCAD '93, pp. 650-653, Nov. 1993.
[6] A.K. Das, "Additive Cellular Automata: Theory and Application as a Built-in Self-test Structure," PhD thesis, IIT, Kharagpur, India, 1990.
[7] A. Das and P.P. Chaudhuri, “Pseudo-Exhaustive Test Pattern Generation Using Cellular Automata,” IEEE Trans. Computers, Vol. 42, No. 3, Mar. 1993, pp. 340-352.
[8] S. Devadas and K. Keutzer, "A Unified Approach to the Synthesis of Fully Testable Sequential Machines," IEEE Trans. Computer-Aided Design, vol. 10, no. 1, Jan. 1991.
[9] S. Devadas, H.K.T. Ma, A.R. Newton, and A.S. Vincentelli, "Mustang: State Assignment of Finite State Machines for Optimalmulti Level Logic Implementations," Proc. ICCAD, Nov. 1987.
[10] S. Devadas, H.K.T. Ma, A.R. Newton, and A.S. Vincentelli, "A Synthesis and Optimization Procedure for Fully and Easily Testable Sequential Machines," IEEE Trans. Computer-Aided Design, Oct. 1989.
[11] B. Elspas, "The Theory of Autonomos Linear Sequential Networks," TRE Trans. Circuits, vol. 6, no. 1, pp. 45-60, Mar. 1959.
[12] B. Eshermann and H.J. Wunderlich, "Optimised Synthesis of Self-testable Finite Machines," Proc. FTCS-20, pp. 390-397, June 1990.
[13] F.R. Gantmatcher, The Theory of Matrices, vol. I. New York: Chelsea Publishing Co., 1959.
[14] S.W. Golomb, Shift Register Sequences. Aegean Park Press, 1982.
[15] P.D. Hortensius, R.D. McLeod, and H.C. Card, Parallel Random Number Generation for VLSI Systems using Cellular Automata IEEE Trans. Computers, vol. 38, no. 10, pp. 1466-1473, Oct. 1989.
[16] H.K.T. Ma, S. Devadas et al., "An Incomplete Scan Design Approach to Test Generation for Sequential Machines," Proc. Int'l Test Conf., 1988.
[17] B. Mitra, S. Misra, and P. Pal Chaudhuri, "A System for Synthesis of Sequential Machines with Built-in Testability," Proc. CICC,San Diego, May 1991.
[18] S. Nandi, B.K. Kar, and P. Pal Chaudhuri, "Theory and Application of Cellular Automata in Cryptography," IEEE Trans. Computers, vol. 43, no. 12, pp. 1,346-1,357, Dec. 1994.
[19] W. Pries, A. Thanailakis, and H.C. Card, "Group Properties of Cellular Automata and VLSI Applications," IEEE Trans. Computers, vol. 35, no. 12, pp. 1,013-1,024, Dec. 1986.
[20] M. Serra et al., "The Analysis of One-Dimensional Linear Cellular Automata and Their Aliasing Properties," IEEE Trans. Computer-Aided Design, vol. 9, no. 7, pp. 767-778, July 1990.
[21] S. Wolfram, "Statistical Mechanics of Cellular Automata," Revised Modern Physics, vol. 55, no. 3, pp. 601-644, July 1983.

Index Terms:
Cellular automata, synthesis for testability (SFT), testable sequential machines.
Citation:
Supratik Chakraborty, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri, "Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines," IEEE Transactions on Computers, vol. 45, no. 7, pp. 769-781, July 1996, doi:10.1109/12.508316
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